[llvm] b904166 - [RISCV][GISel] Remove -disable-gisel-legality-check from scalar tests. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 13 12:00:49 PST 2024
Author: Craig Topper
Date: 2024-11-13T11:58:24-08:00
New Revision: b904166aa0cf9a00440076911056ed81d01dfe59
URL: https://github.com/llvm/llvm-project/commit/b904166aa0cf9a00440076911056ed81d01dfe59
DIFF: https://github.com/llvm/llvm-project/commit/b904166aa0cf9a00440076911056ed81d01dfe59.diff
LOG: [RISCV][GISel] Remove -disable-gisel-legality-check from scalar tests. NFC
Adjust a couple tests so they can pass the check.
Added:
Modified:
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
index 1677c734eb9171..1b6684dc42397c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
index 701f3d49ed85b6..cef929f1e05be1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
index 7e02e7d25d2da9..1296d5f3cbfa12 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
index c162ac0b6e996c..98c0707128a418 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
index e6a8f4100f4e76..9cc0b579ed48e7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
---
@@ -8,25 +8,19 @@ name: anyext_i32_i64
legalized: true
body: |
bb.0.entry:
- liveins: $x10, $x11
+ liveins: $x10
; RV64I-LABEL: name: anyext_i32_i64
- ; RV64I: liveins: $x10, $x11
+ ; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
- ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
- ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[ADD]](s32)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[TRUNC]](s32)
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %2(s64)
- %3:_(s64) = COPY $x11
- %1:_(s32) = G_TRUNC %3(s64)
- %4:_(s32) = G_ADD %0, %1
- %5:_(s64) = G_ANYEXT %4(s32)
+ %5:_(s64) = G_ANYEXT %0(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
@@ -36,25 +30,19 @@ name: sext_i32_i64
legalized: true
body: |
bb.0.entry:
- liveins: $x10, $x11
+ liveins: $x10
; RV64I-LABEL: name: sext_i32_i64
- ; RV64I: liveins: $x10, $x11
+ ; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
- ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
- ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; RV64I-NEXT: [[SEXT:%[0-9]+]]:gprb(s64) = G_SEXT [[ADD]](s32)
+ ; RV64I-NEXT: [[SEXT:%[0-9]+]]:gprb(s64) = G_SEXT [[TRUNC]](s32)
; RV64I-NEXT: $x10 = COPY [[SEXT]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %2(s64)
- %3:_(s64) = COPY $x11
- %1:_(s32) = G_TRUNC %3(s64)
- %4:_(s32) = G_ADD %0, %1
- %5:_(s64) = G_SEXT %4(s32)
+ %5:_(s64) = G_SEXT %0(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
@@ -64,25 +52,19 @@ name: zext_i32_i64
legalized: true
body: |
bb.0.entry:
- liveins: $x10, $x11
+ liveins: $x10
; RV64I-LABEL: name: zext_i32_i64
- ; RV64I: liveins: $x10, $x11
+ ; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
- ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
- ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:gprb(s64) = G_ZEXT [[ADD]](s32)
+ ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:gprb(s64) = G_ZEXT [[TRUNC]](s32)
; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %2(s64)
- %3:_(s64) = COPY $x11
- %1:_(s32) = G_TRUNC %3(s64)
- %4:_(s32) = G_ADD %0, %1
- %5:_(s64) = G_ZEXT %4(s32)
+ %5:_(s64) = G_ZEXT %0(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
index 835f026d187a24..7dee1370f283d1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
index 1ecee1643daac9..e7f95003737211 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
index 8cea5fd19007c9..b43371ad40d723 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
index 36146c158d8a59..c4196b06e33192 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
index 81e8a5a6c8303f..45e96b152f875c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
index 357c1895b158e2..77fb05edd7ec34 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
---
@@ -122,10 +122,16 @@ body: |
bb.0:
liveins: $x10
+ ; RV64I-LABEL: name: zextload_i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; RV64I-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
- %3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
- %2:_(s64) = G_ANYEXT %3(s32)
- $x10 = COPY %2(s64)
+ %3:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %3(s64)
PseudoRET implicit $x10
...
@@ -141,14 +147,12 @@ body: |
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; RV64I-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
- %3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
- %2:_(s64) = G_ANYEXT %3(s32)
- $x10 = COPY %2(s64)
+ %3:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %3(s64)
PseudoRET implicit $x10
...
@@ -181,10 +185,16 @@ body: |
bb.0:
liveins: $x10
+ ; RV64I-LABEL: name: sextload_i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; RV64I-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
- %3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
- %2:_(s64) = G_ANYEXT %3(s32)
- $x10 = COPY %2(s64)
+ %3:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %3(s64)
PseudoRET implicit $x10
...
@@ -200,14 +210,12 @@ body: |
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[SEXTLOAD]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; RV64I-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
- %3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
- %2:_(s64) = G_ANYEXT %3(s32)
- $x10 = COPY %2(s64)
+ %3:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %3(s64)
PseudoRET implicit $x10
...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
index 123b6b9649837b..715ba22dc99bce 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
index 661f1ed61df603..2fb680fd15d8fe 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
index b8bedfae987d31..8feeebf37107ea 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
index e7db66b37bd2bf..a1537ac0173e45 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
index fe5c799187480d..5252b25b6f3b64 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
index df3f6319debfa5..47d396f4eb3812 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
index 903cc868e69e4e..544c3bb06a106e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
index 3ea9a51dc4203f..c3475dd64789aa 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
index e20d5f7fbb74fb..9ed3b678e9711e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
@@ -1,9 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefixes=RV32 %s
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefixes=RV64 %s
...
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