[llvm] 62441b9 - [RISCV][GISel] Add instruction selection mir test for f32/f64 fp load/store. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-11-13T11:35:28-08:00
New Revision: 62441b9f30a65b2708697f06333cb8bc777cebe9

URL: https://github.com/llvm/llvm-project/commit/62441b9f30a65b2708697f06333cb8bc777cebe9
DIFF: https://github.com/llvm/llvm-project/commit/62441b9f30a65b2708697f06333cb8bc777cebe9.diff

LOG: [RISCV][GISel] Add instruction selection mir test for f32/f64 fp load/store. NFC

We had a regbank-select test but not an instruction selection test.

Added: 
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
new file mode 100644
index 00000000000000..23640d39be4d33
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+
+---
+name:            fp_store_f32
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $f10_f
+
+    ; CHECK-LABEL: name: fp_store_f32
+    ; CHECK: liveins: $x10, $f10_f
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
+    ; CHECK-NEXT: FSW [[COPY1]], [[COPY]], 0 :: (store (s32))
+    ; CHECK-NEXT: PseudoRET
+    %0:gprb(p0) = COPY $x10
+    %1:fprb(s32) = COPY $f10_f
+    G_STORE %1(s32), %0(p0) :: (store (s32))
+    PseudoRET
+
+...
+---
+name:            fp_store_f64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $f10_d
+
+    ; CHECK-LABEL: name: fp_store_f64
+    ; CHECK: liveins: $x10, $f10_d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d
+    ; CHECK-NEXT: FSD [[COPY1]], [[COPY]], 0 :: (store (s64))
+    ; CHECK-NEXT: PseudoRET
+    %0:gprb(p0) = COPY $x10
+    %1:fprb(s64) = COPY $f10_d
+    G_STORE %1(s64), %0(p0) :: (store (s64))
+    PseudoRET
+
+...
+---
+name:            fp_load_f32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: fp_load_f32
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[FLW:%[0-9]+]]:fpr32 = FLW [[COPY]], 0 :: (load (s32))
+    ; CHECK-NEXT: $f10_f = COPY [[FLW]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_f
+    %0:gprb(p0) = COPY $x10
+    %1:fprb(s32) = G_LOAD %0(p0) :: (load (s32))
+    $f10_f = COPY %1(s32)
+    PseudoRET implicit $f10_f
+
+...
+---
+name:            fp_load_f64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: fp_load_f64
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[FLD:%[0-9]+]]:fpr64 = FLD [[COPY]], 0 :: (load (s64))
+    ; CHECK-NEXT: $f10_d = COPY [[FLD]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    %0:gprb(p0) = COPY $x10
+    %1:fprb(s64) = G_LOAD %0(p0) :: (load (s64))
+    $f10_d = COPY %1(s64)
+    PseudoRET implicit $f10_d
+
+...