[llvm] [NVPTX] Add patterns for fma.relu.{f16|f16x2|bf16|bf16x2} (PR #114977)
Hugh Delaney via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 13 09:27:34 PST 2024
https://github.com/hdelan updated https://github.com/llvm/llvm-project/pull/114977
>From f5eea93c32e099c60c275b5cf4139b4e07137ef3 Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Tue, 5 Nov 2024 12:25:41 +0000
Subject: [PATCH 01/14] Add patterns for fma.relu.{f16|bf16}
Add patterns to lower fma(a, b, c) > 0 ? fma(a, b, c) : 0 for f16 and
bf16 types.
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 37 +
llvm/test/CodeGen/NVPTX/fma-relu.ll | 920 ++++++++++++++++++++++++
2 files changed, 957 insertions(+)
create mode 100644 llvm/test/CodeGen/NVPTX/fma-relu.ll
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 5f6cba397c5352..39ab54841e8294 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3917,3 +3917,40 @@ def atomic_thread_fence_seq_cst_cta :
def atomic_thread_fence_acq_rel_cta :
NVPTXInst<(outs), (ins), "fence.acq_rel.cta;", []>,
Requires<[hasPTX<60>, hasSM<70>]>;
+
+def fpimm0 : FPImmLeaf<fAny, [{
+ return Imm.isExactlyValue(+0.0);
+}]>;
+
+def FMARELU_F16 :
+ NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
+ "fma.rn.relu.f16 \t$dst, $a, $b, $c;", []>,
+ Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
+def FMARELU_BF16 :
+ NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
+ "fma.rn.relu.bf16 \t$dst, $a, $b, $c;", []>,
+ Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
+def FMARELU_F16_FTZ :
+ NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
+ "fma.rn.relu.ftz.f16 \t$dst, $a, $b, $c;", []>,
+ Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
+def FMARELU_BF16_FTZ :
+ NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
+ "fma.rn.relu.ftz.bf16 \t$dst, $a, $b, $c;", []>,
+ Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
+
+
+// FTZ variants
+def : Pat<(f16 (fmaxnum (fma Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+ (FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
+ Requires<[doF32FTZ, allowUnsafeFPMath]>;
+def : Pat<(bf16 (fmaxnum (fma Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+ (FMARELU_BF16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
+ Requires<[doF32FTZ, allowUnsafeFPMath]>;
+// No FTZ
+def : Pat<(f16 (fmaxnum (fma Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+ (FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
+ Requires<[allowUnsafeFPMath]>;
+def : Pat<(bf16 (fmaxnum (fma Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+ (FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
+ Requires<[allowUnsafeFPMath]>;
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu.ll b/llvm/test/CodeGen/NVPTX/fma-relu.ll
new file mode 100644
index 00000000000000..3d95a4df2d3308
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/fma-relu.ll
@@ -0,0 +1,920 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; Using FTZ should emit fma.ftz.relu
+; RUN: llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK-FTZ
+; RUN: %if ptxas %{ llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; Don't contract FMAs
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -nvptx-fma-level=0 | FileCheck %s --check-prefixes=CHECK-NO-FMA-CONTRACTION
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -nvptx-fma-level=2 | FileCheck %s --check-prefixes=CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH
+
+; SM < 80 or (which needs PTX version >= 70) should not emit fma{.ftz}.relu
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 | FileCheck %s --check-prefixes=CHECK-SM70
+
+define half @fma_f16_unsafe(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_unsafe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_unsafe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
+ %2 = fcmp ogt half %1, 0.0
+ %3 = select i1 %2, half %1, half 0.0
+ ret half %3
+}
+
+define half @fma_f16_maxnum_unsafe(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_maxnum_unsafe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_maxnum_unsafe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
+ %2 = call half @llvm.maxnum.f16(half %1, half 0.0)
+ ret half %2
+}
+
+define half @fma_f16_expanded_unsafe(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_expanded_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_expanded_unsafe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_expanded_unsafe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul half %a, %b
+ %2 = fadd half %1, %c
+ %3 = fcmp ogt half %2, 0.0
+ %4 = select i1 %3, half %2, half 0.0
+ ret half %4
+}
+
+define half @fma_f16_expanded_safe(half %a, half %b, half %c) {
+; CHECK-LABEL: fma_f16_expanded_safe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
+; CHECK-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
+; CHECK-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-NEXT: mov.b16 %rs6, 0x0000;
+; CHECK-NEXT: max.f16 %rs7, %rs5, %rs6;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_safe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<8>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
+; CHECK-FTZ-NEXT: mul.rn.ftz.f16 %rs3, %rs1, %rs2;
+; CHECK-FTZ-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
+; CHECK-FTZ-NEXT: add.rn.ftz.f16 %rs5, %rs3, %rs4;
+; CHECK-FTZ-NEXT: mov.b16 %rs6, 0x0000;
+; CHECK-FTZ-NEXT: max.ftz.f16 %rs7, %rs5, %rs6;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_expanded_safe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<8>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b16 %rs6, 0x0000;
+; CHECK-NO-FMA-CONTRACTION-NEXT: max.f16 %rs7, %rs5, %rs6;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_expanded_safe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<8>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mul.f16 %rs3, %rs1, %rs2;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: add.f16 %rs5, %rs3, %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b16 %rs6, 0x0000;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: max.f16 %rs7, %rs5, %rs6;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_safe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<7>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
+; CHECK-SM70-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-SM70-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
+; CHECK-SM70-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs5;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs6, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs6;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul half %a, %b
+ %2 = fadd half %1, %c
+ %3 = fcmp ogt half %2, 0.0
+ %4 = select i1 %3, half %2, half 0.0
+ ret half %4
+}
+
+define half @fma_f16_expanded_maxnum_unsafe(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul half %a, %b
+ %2 = fadd half %1, %c
+ %3 = call half @llvm.maxnum.f16(half %2, half 0.0)
+ ret half %3
+}
+
+define bfloat @fma_bf16_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_unsafe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_unsafe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_unsafe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_unsafe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_unsafe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
+ %2 = fcmp ogt bfloat %1, 0.0
+ %3 = select i1 %2, bfloat %1, bfloat 0.0
+ ret bfloat %3
+}
+
+define bfloat @fma_bf16_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
+ %2 = call bfloat @llvm.maxnum.bf16(bfloat %1, bfloat 0.0)
+ ret bfloat %2
+}
+
+define bfloat @fma_bf16_expanded_safe(bfloat %a, bfloat %b, bfloat %c) {
+; CHECK-LABEL: fma_bf16_expanded_safe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<6>;
+; CHECK-NEXT: .reg .b32 %r<9>;
+; CHECK-NEXT: .reg .f32 %f<7>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-NEXT: mov.b32 %f1, %r2;
+; CHECK-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-NEXT: mov.b32 %f2, %r4;
+; CHECK-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-NEXT: mov.b32 %f4, %r6;
+; CHECK-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
+; CHECK-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-NEXT: mov.b32 %f5, %r8;
+; CHECK-NEXT: add.rn.f32 %f6, %f4, %f5;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
+; CHECK-NEXT: mov.b16 %rs4, 0x0000;
+; CHECK-NEXT: max.bf16 %rs5, %rs3, %rs4;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_safe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<6>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<9>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<7>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
+; CHECK-FTZ-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-FTZ-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f2, %r4;
+; CHECK-FTZ-NEXT: mul.rn.ftz.f32 %f3, %f2, %f1;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f4, %r6;
+; CHECK-FTZ-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
+; CHECK-FTZ-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f5, %r8;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f6, %f4, %f5;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
+; CHECK-FTZ-NEXT: mov.b16 %rs4, 0x0000;
+; CHECK-FTZ-NEXT: max.bf16 %rs5, %rs3, %rs4;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_expanded_safe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<6>;
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b32 %r<9>;
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .f32 %f<7>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b32 %f1, %r2;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b32 %f2, %r4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; CHECK-NO-FMA-CONTRACTION-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-NO-FMA-CONTRACTION-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b32 %f4, %r6;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b32 %f5, %r8;
+; CHECK-NO-FMA-CONTRACTION-NEXT: add.rn.f32 %f6, %f4, %f5;
+; CHECK-NO-FMA-CONTRACTION-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
+; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b16 %rs4, 0x0000;
+; CHECK-NO-FMA-CONTRACTION-NEXT: max.bf16 %rs5, %rs3, %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_expanded_safe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<6>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b32 %r<9>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .f32 %f<7>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b32 %f1, %r2;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b32 %f2, %r4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mul.f32 %f3, %f2, %f1;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b32 %f4, %r6;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b32 %f5, %r8;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: add.f32 %f6, %f4, %f5;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b16 %rs4, 0x0000;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: max.bf16 %rs5, %rs3, %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_safe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<4>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<27>;
+; CHECK-SM70-NEXT: .reg .f32 %f<9>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r5, %f3;
+; CHECK-SM70-NEXT: bfe.u32 %r6, %r5, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r7, %r6, %r5;
+; CHECK-SM70-NEXT: add.s32 %r8, %r7, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f3, %f3;
+; CHECK-SM70-NEXT: or.b32 %r9, %r5, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r10, %r9, %r8, %p1;
+; CHECK-SM70-NEXT: and.b32 %r11, %r10, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f4, %r11;
+; CHECK-SM70-NEXT: ld.param.u16 %r12, [fma_bf16_expanded_safe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r13, %r12, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: add.rn.f32 %f6, %f4, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: and.b32 %r20, %r19, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r20;
+; CHECK-SM70-NEXT: max.f32 %f8, %f7, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r21, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r22, %r21, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r23, %r22, %r21;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r25, %r21, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r26, %r25, %r24, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r26; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul bfloat %a, %b
+ %2 = fadd bfloat %1, %c
+ %3 = fcmp ogt bfloat %2, 0.0
+ %4 = select i1 %3, bfloat %2, bfloat 0.0
+ ret bfloat %4
+}
+
+define bfloat @fma_bf16_expanded_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_expanded_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_expanded_unsafe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_expanded_unsafe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul bfloat %a, %b
+ %2 = fadd bfloat %1, %c
+ %3 = fcmp ogt bfloat %2, 0.0
+ %4 = select i1 %3, bfloat %2, bfloat 0.0
+ ret bfloat %4
+}
+
+define bfloat @fma_bf16_expanded_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK-NO-FMA-CONTRACTION: {
+; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
+; CHECK-NO-FMA-CONTRACTION-EMPTY:
+; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
+;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul bfloat %a, %b
+ %2 = fadd bfloat %1, %c
+ %3 = call bfloat @llvm.maxnum.bf16(bfloat %2, bfloat 0.0)
+ ret bfloat %3
+}
+
+attributes #0 = { "unsafe-fp-math"="true" }
>From c793bfd09af8da0eda9a35422304f0509b0a6874 Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Thu, 7 Nov 2024 10:25:13 +0000
Subject: [PATCH 02/14] Make sure FMA only has one use, update tests
FMA relu should only be emitted if the FMA node has a single use. This
should limit register pressure in some cases do avoid computing FMA as
well as FMA.relu.
Also split tests into two files, one using FMA contraction and the other
using the FMA intrinsic.
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 17 +-
llvm/test/CodeGen/NVPTX/fma-relu-contract.ll | 600 ++++++++++++
.../CodeGen/NVPTX/fma-relu-fma-intrinsic.ll | 400 ++++++++
llvm/test/CodeGen/NVPTX/fma-relu.ll | 920 ------------------
4 files changed, 1011 insertions(+), 926 deletions(-)
create mode 100644 llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
create mode 100644 llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/fma-relu.ll
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 39ab54841e8294..5a4fb90aba2a32 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3932,25 +3932,30 @@ def FMARELU_BF16 :
Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
def FMARELU_F16_FTZ :
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
- "fma.rn.relu.ftz.f16 \t$dst, $a, $b, $c;", []>,
+ "fma.rn.ftz.relu.f16 \t$dst, $a, $b, $c;", []>,
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
def FMARELU_BF16_FTZ :
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
- "fma.rn.relu.ftz.bf16 \t$dst, $a, $b, $c;", []>,
+ "fma.rn.ftz.relu.bf16 \t$dst, $a, $b, $c;", []>,
Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
+// Patterns will only be used if FMA has a single use, in order to mitigate register pressure
+def NVPTX_fma_oneuse : PatFrag<(ops node:$a, node:$b, node:$c),
+ (fma node:$a, node:$b, node:$c), [{
+ return N->hasOneUse();
+}]>;
// FTZ variants
-def : Pat<(f16 (fmaxnum (fma Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
(FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
-def : Pat<(bf16 (fmaxnum (fma Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
(FMARELU_BF16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
// No FTZ
-def : Pat<(f16 (fmaxnum (fma Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
(FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[allowUnsafeFPMath]>;
-def : Pat<(bf16 (fmaxnum (fma Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
(FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[allowUnsafeFPMath]>;
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
new file mode 100644
index 00000000000000..74d5ae45997e89
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
@@ -0,0 +1,600 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; Using FTZ should emit fma.ftz.relu
+; RUN: llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK-FTZ
+; RUN: %if ptxas %{ llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; SM < 80 or (which needs PTX version >= 70) should not emit fma{.ftz}.relu
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 | FileCheck %s --check-prefixes=CHECK-SM70
+
+define half @fma_f16_expanded_unsafe(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_expanded_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul half %a, %b
+ %2 = fadd half %1, %c
+ %3 = fcmp ogt half %2, 0.0
+ %4 = select i1 %3, half %2, half 0.0
+ ret half %4
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define half @fma_f16_expanded_unsafe_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<10>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-NEXT: max.f16 %rs6, %rs4, %rs5;
+; CHECK-NEXT: mov.b16 %rs7, 0x4700;
+; CHECK-NEXT: add.f16 %rs8, %rs4, %rs7;
+; CHECK-NEXT: add.f16 %rs9, %rs6, %rs8;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs9;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<10>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-FTZ-NEXT: max.ftz.f16 %rs6, %rs4, %rs5;
+; CHECK-FTZ-NEXT: mov.b16 %rs7, 0x4700;
+; CHECK-FTZ-NEXT: add.ftz.f16 %rs8, %rs4, %rs7;
+; CHECK-FTZ-NEXT: add.ftz.f16 %rs9, %rs6, %rs8;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs9;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<9>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: mov.b16 %rs6, 0x4700;
+; CHECK-SM70-NEXT: add.f16 %rs7, %rs4, %rs6;
+; CHECK-SM70-NEXT: add.f16 %rs8, %rs5, %rs7;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs8;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul half %a, %b
+ %2 = fadd half %1, %c
+ %3 = fcmp ogt half %2, 0.0
+ %4 = select i1 %3, half %2, half 0.0
+ %5 = fadd half %2, 7.0
+ %6 = fadd half %4, %5
+ ret half %6
+}
+
+define half @fma_f16_expanded_safe(half %a, half %b, half %c) {
+; CHECK-LABEL: fma_f16_expanded_safe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
+; CHECK-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
+; CHECK-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-NEXT: mov.b16 %rs6, 0x0000;
+; CHECK-NEXT: max.f16 %rs7, %rs5, %rs6;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_safe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<8>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
+; CHECK-FTZ-NEXT: mul.rn.ftz.f16 %rs3, %rs1, %rs2;
+; CHECK-FTZ-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
+; CHECK-FTZ-NEXT: add.rn.ftz.f16 %rs5, %rs3, %rs4;
+; CHECK-FTZ-NEXT: mov.b16 %rs6, 0x0000;
+; CHECK-FTZ-NEXT: max.ftz.f16 %rs7, %rs5, %rs6;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_safe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<7>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
+; CHECK-SM70-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-SM70-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
+; CHECK-SM70-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs5;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs6, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs6;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul half %a, %b
+ %2 = fadd half %1, %c
+ %3 = fcmp ogt half %2, 0.0
+ %4 = select i1 %3, half %2, half 0.0
+ ret half %4
+}
+
+define half @fma_f16_expanded_maxnum_unsafe(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul half %a, %b
+ %2 = fadd half %1, %c
+ %3 = call half @llvm.maxnum.f16(half %2, half 0.0)
+ ret half %3
+}
+
+define bfloat @fma_bf16_expanded_safe(bfloat %a, bfloat %b, bfloat %c) {
+; CHECK-LABEL: fma_bf16_expanded_safe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<6>;
+; CHECK-NEXT: .reg .b32 %r<9>;
+; CHECK-NEXT: .reg .f32 %f<7>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-NEXT: mov.b32 %f1, %r2;
+; CHECK-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-NEXT: mov.b32 %f2, %r4;
+; CHECK-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-NEXT: mov.b32 %f4, %r6;
+; CHECK-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
+; CHECK-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-NEXT: mov.b32 %f5, %r8;
+; CHECK-NEXT: add.rn.f32 %f6, %f4, %f5;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
+; CHECK-NEXT: mov.b16 %rs4, 0x0000;
+; CHECK-NEXT: max.bf16 %rs5, %rs3, %rs4;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_safe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<6>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<9>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<7>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
+; CHECK-FTZ-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-FTZ-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f2, %r4;
+; CHECK-FTZ-NEXT: mul.rn.ftz.f32 %f3, %f2, %f1;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f4, %r6;
+; CHECK-FTZ-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
+; CHECK-FTZ-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f5, %r8;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f6, %f4, %f5;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
+; CHECK-FTZ-NEXT: mov.b16 %rs4, 0x0000;
+; CHECK-FTZ-NEXT: max.bf16 %rs5, %rs3, %rs4;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_safe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<4>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<27>;
+; CHECK-SM70-NEXT: .reg .f32 %f<9>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r5, %f3;
+; CHECK-SM70-NEXT: bfe.u32 %r6, %r5, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r7, %r6, %r5;
+; CHECK-SM70-NEXT: add.s32 %r8, %r7, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f3, %f3;
+; CHECK-SM70-NEXT: or.b32 %r9, %r5, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r10, %r9, %r8, %p1;
+; CHECK-SM70-NEXT: and.b32 %r11, %r10, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f4, %r11;
+; CHECK-SM70-NEXT: ld.param.u16 %r12, [fma_bf16_expanded_safe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r13, %r12, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: add.rn.f32 %f6, %f4, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: and.b32 %r20, %r19, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r20;
+; CHECK-SM70-NEXT: max.f32 %f8, %f7, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r21, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r22, %r21, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r23, %r22, %r21;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r25, %r21, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r26, %r25, %r24, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r26; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul bfloat %a, %b
+ %2 = fadd bfloat %1, %c
+ %3 = fcmp ogt bfloat %2, 0.0
+ %4 = select i1 %3, bfloat %2, bfloat 0.0
+ ret bfloat %4
+}
+
+define bfloat @fma_bf16_expanded_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_expanded_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul bfloat %a, %b
+ %2 = fadd bfloat %1, %c
+ %3 = fcmp ogt bfloat %2, 0.0
+ %4 = select i1 %3, bfloat %2, bfloat 0.0
+ ret bfloat %4
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define bfloat @fma_bf16_expanded_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<12>;
+; CHECK-NEXT: .reg .b32 %r<7>;
+; CHECK-NEXT: .reg .f32 %f<6>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-NEXT: max.bf16 %rs6, %rs4, %rs5;
+; CHECK-NEXT: cvt.u32.u16 %r1, %rs4;
+; CHECK-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-NEXT: mov.b32 %f1, %r2;
+; CHECK-NEXT: add.f32 %f2, %f1, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs8, %f2;
+; CHECK-NEXT: cvt.u32.u16 %r3, %rs6;
+; CHECK-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-NEXT: mov.b32 %f3, %r4;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs8;
+; CHECK-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-NEXT: mov.b32 %f4, %r6;
+; CHECK-NEXT: add.f32 %f5, %f3, %f4;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs11, %f5;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<12>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<7>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<6>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-FTZ-NEXT: max.bf16 %rs6, %rs4, %rs5;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r1, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f2, %f1, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs8, %f2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r3, %rs6;
+; CHECK-FTZ-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f3, %r4;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs8;
+; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f4, %r6;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f5, %f3, %f4;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs11, %f5;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<34>;
+; CHECK-SM70-NEXT: .reg .f32 %f<11>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: add.f32 %f7, %f5, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r20, %f7;
+; CHECK-SM70-NEXT: bfe.u32 %r21, %r20, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r22, %r21, %r20;
+; CHECK-SM70-NEXT: add.s32 %r23, %r22, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f7, %f7;
+; CHECK-SM70-NEXT: or.b32 %r24, %r20, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r25, %r24, %r23, %p3;
+; CHECK-SM70-NEXT: and.b32 %r26, %r25, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f8, %r26;
+; CHECK-SM70-NEXT: and.b32 %r27, %r19, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r27;
+; CHECK-SM70-NEXT: add.f32 %f10, %f9, %f8;
+; CHECK-SM70-NEXT: mov.b32 %r28, %f10;
+; CHECK-SM70-NEXT: bfe.u32 %r29, %r28, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r30, %r29, %r28;
+; CHECK-SM70-NEXT: add.s32 %r31, %r30, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f10, %f10;
+; CHECK-SM70-NEXT: or.b32 %r32, %r28, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r33, %r32, %r31, %p4;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r33; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul bfloat %a, %b
+ %2 = fadd bfloat %1, %c
+ %3 = fcmp ogt bfloat %2, 0.0
+ %4 = select i1 %3, bfloat %2, bfloat 0.0
+ %5 = fadd bfloat %2, 7.0
+ %6 = fadd bfloat %4, %5
+ ret bfloat %6
+}
+
+define bfloat @fma_bf16_expanded_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul bfloat %a, %b
+ %2 = fadd bfloat %1, %c
+ %3 = call bfloat @llvm.maxnum.bf16(bfloat %2, bfloat 0.0)
+ ret bfloat %3
+}
+
+attributes #0 = { "unsafe-fp-math"="true" }
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
new file mode 100644
index 00000000000000..3e114e02d463b0
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
@@ -0,0 +1,400 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; Using FTZ should emit fma.ftz.relu
+; RUN: llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK-FTZ
+; RUN: %if ptxas %{ llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; SM < 80 or (which needs PTX version >= 70) should not emit fma{.ftz}.relu
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 | FileCheck %s --check-prefixes=CHECK-SM70
+
+define half @fma_f16_unsafe(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
+ %2 = fcmp ogt half %1, 0.0
+ %3 = select i1 %2, half %1, half 0.0
+ ret half %3
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define half @fma_f16_unsafe_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_unsafe_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: mov.b16 %rs5, 0x4700;
+; CHECK-NEXT: add.f16 %rs6, %rs4, %rs5;
+; CHECK-NEXT: add.f16 %rs7, %rs6, %rs4;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<8>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x4700;
+; CHECK-FTZ-NEXT: add.ftz.f16 %rs6, %rs4, %rs5;
+; CHECK-FTZ-NEXT: add.ftz.f16 %rs7, %rs6, %rs4;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_unsafe_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<8>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: mov.b16 %rs5, 0x4700;
+; CHECK-SM70-NEXT: add.f16 %rs6, %rs4, %rs5;
+; CHECK-SM70-NEXT: add.f16 %rs7, %rs6, %rs4;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-SM70-NEXT: ret;
+ %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
+ %2 = fcmp ogt half %1, 0.0
+ %3 = select i1 %2, half %1, half 0.0
+ %4 = fadd half %1, 7.0
+ %5 = fadd half %4, %1
+ ret half %5
+}
+
+define half @fma_f16_maxnum_unsafe(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
+ %2 = call half @llvm.maxnum.f16(half %1, half 0.0)
+ ret half %2
+}
+
+define bfloat @fma_bf16_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_unsafe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_unsafe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_unsafe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
+ %2 = fcmp ogt bfloat %1, 0.0
+ %3 = select i1 %2, bfloat %1, bfloat 0.0
+ ret bfloat %3
+}
+
+; FMA_relu shouldn't be selected if the FMA operation has multiple uses
+define bfloat @fma_bf16_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_unsafe_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<9>;
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: cvt.u32.u16 %r1, %rs4;
+; CHECK-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-NEXT: mov.b32 %f1, %r2;
+; CHECK-NEXT: add.f32 %f2, %f1, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs6, %f2;
+; CHECK-NEXT: cvt.u32.u16 %r3, %rs6;
+; CHECK-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-NEXT: mov.b32 %f3, %r4;
+; CHECK-NEXT: add.f32 %f4, %f3, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs8, %f4;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs8;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<9>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r1, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f2, %f1, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs6, %f2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r3, %rs6;
+; CHECK-FTZ-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f3, %r4;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f4, %f3, %f1;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs8, %f4;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs8;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_unsafe_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<4>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<27>;
+; CHECK-SM70-NEXT: .reg .f32 %f<9>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: add.f32 %f6, %f5, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: and.b32 %r20, %r19, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r20;
+; CHECK-SM70-NEXT: add.f32 %f8, %f7, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r21, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r22, %r21, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r23, %r22, %r21;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r25, %r21, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r26, %r25, %r24, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r26; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
+ %2 = fcmp ogt bfloat %1, 0.0
+ %3 = select i1 %2, bfloat %1, bfloat 0.0
+ %4 = fadd bfloat %1, 7.0
+ %5 = fadd bfloat %4, %1
+ ret bfloat %5
+}
+
+define bfloat @fma_bf16_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
+ %2 = call bfloat @llvm.maxnum.bf16(bfloat %1, bfloat 0.0)
+ ret bfloat %2
+}
+
+attributes #0 = { "unsafe-fp-math"="true" }
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu.ll b/llvm/test/CodeGen/NVPTX/fma-relu.ll
deleted file mode 100644
index 3d95a4df2d3308..00000000000000
--- a/llvm/test/CodeGen/NVPTX/fma-relu.ll
+++ /dev/null
@@ -1,920 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
-
-; Using FTZ should emit fma.ftz.relu
-; RUN: llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK-FTZ
-; RUN: %if ptxas %{ llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
-
-; Don't contract FMAs
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -nvptx-fma-level=0 | FileCheck %s --check-prefixes=CHECK-NO-FMA-CONTRACTION
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -nvptx-fma-level=2 | FileCheck %s --check-prefixes=CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH
-
-; SM < 80 or (which needs PTX version >= 70) should not emit fma{.ftz}.relu
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 | FileCheck %s --check-prefixes=CHECK-SM70
-
-define half @fma_f16_unsafe(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_unsafe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
-; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_f16_unsafe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.relu.ftz.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_unsafe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_unsafe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_f16_unsafe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
-; CHECK-SM70-NEXT: .reg .f32 %f<3>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
-; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
-; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
-; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-SM70-NEXT: ret;
- %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
- %2 = fcmp ogt half %1, 0.0
- %3 = select i1 %2, half %1, half 0.0
- ret half %3
-}
-
-define half @fma_f16_maxnum_unsafe(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_maxnum_unsafe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
-; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_f16_maxnum_unsafe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.relu.ftz.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_maxnum_unsafe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_maxnum_unsafe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_f16_maxnum_unsafe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
-; CHECK-SM70-NEXT: .reg .f32 %f<3>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
-; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
-; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
-; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-SM70-NEXT: ret;
- %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
- %2 = call half @llvm.maxnum.f16(half %1, half 0.0)
- ret half %2
-}
-
-define half @fma_f16_expanded_unsafe(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_expanded_unsafe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
-; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_f16_expanded_unsafe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.relu.ftz.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_expanded_unsafe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_expanded_unsafe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_f16_expanded_unsafe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
-; CHECK-SM70-NEXT: .reg .f32 %f<3>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
-; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
-; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
-; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-SM70-NEXT: ret;
- %1 = fmul half %a, %b
- %2 = fadd half %1, %c
- %3 = fcmp ogt half %2, 0.0
- %4 = select i1 %3, half %2, half 0.0
- ret half %4
-}
-
-define half @fma_f16_expanded_safe(half %a, half %b, half %c) {
-; CHECK-LABEL: fma_f16_expanded_safe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
-; CHECK-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
-; CHECK-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
-; CHECK-NEXT: mov.b16 %rs6, 0x0000;
-; CHECK-NEXT: max.f16 %rs7, %rs5, %rs6;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs7;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_f16_expanded_safe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<8>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
-; CHECK-FTZ-NEXT: mul.rn.ftz.f16 %rs3, %rs1, %rs2;
-; CHECK-FTZ-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
-; CHECK-FTZ-NEXT: add.rn.ftz.f16 %rs5, %rs3, %rs4;
-; CHECK-FTZ-NEXT: mov.b16 %rs6, 0x0000;
-; CHECK-FTZ-NEXT: max.ftz.f16 %rs7, %rs5, %rs6;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs7;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_expanded_safe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<8>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b16 %rs6, 0x0000;
-; CHECK-NO-FMA-CONTRACTION-NEXT: max.f16 %rs7, %rs5, %rs6;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs7;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_expanded_safe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<8>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mul.f16 %rs3, %rs1, %rs2;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: add.f16 %rs5, %rs3, %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b16 %rs6, 0x0000;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: max.f16 %rs7, %rs5, %rs6;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs7;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_f16_expanded_safe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .b16 %rs<7>;
-; CHECK-SM70-NEXT: .reg .f32 %f<3>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
-; CHECK-SM70-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
-; CHECK-SM70-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
-; CHECK-SM70-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
-; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs5;
-; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
-; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs6, %f2;
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs6;
-; CHECK-SM70-NEXT: ret;
- %1 = fmul half %a, %b
- %2 = fadd half %1, %c
- %3 = fcmp ogt half %2, 0.0
- %4 = select i1 %3, half %2, half 0.0
- ret half %4
-}
-
-define half @fma_f16_expanded_maxnum_unsafe(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_expanded_maxnum_unsafe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
-; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_f16_expanded_maxnum_unsafe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.relu.ftz.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_f16_expanded_maxnum_unsafe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_f16_expanded_maxnum_unsafe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_f16_expanded_maxnum_unsafe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
-; CHECK-SM70-NEXT: .reg .f32 %f<3>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
-; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
-; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
-; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-SM70-NEXT: ret;
- %1 = fmul half %a, %b
- %2 = fadd half %1, %c
- %3 = call half @llvm.maxnum.f16(half %2, half 0.0)
- ret half %3
-}
-
-define bfloat @fma_bf16_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_unsafe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
-; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_bf16_unsafe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.relu.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_unsafe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_unsafe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_bf16_unsafe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .pred %p<3>;
-; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM70-NEXT: .reg .b32 %r<20>;
-; CHECK-SM70-NEXT: .reg .f32 %f<7>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_unsafe_param_2];
-; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_unsafe_param_1];
-; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_unsafe_param_0];
-; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
-; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
-; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
-; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
-; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
-; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
-; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
-; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
-; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
-; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
-; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
-; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
-; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
-; CHECK-SM70-NEXT: ret;
- %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
- %2 = fcmp ogt bfloat %1, 0.0
- %3 = select i1 %2, bfloat %1, bfloat 0.0
- ret bfloat %3
-}
-
-define bfloat @fma_bf16_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_maxnum_unsafe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
-; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_bf16_maxnum_unsafe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.relu.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_maxnum_unsafe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_maxnum_unsafe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_bf16_maxnum_unsafe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .pred %p<3>;
-; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM70-NEXT: .reg .b32 %r<20>;
-; CHECK-SM70-NEXT: .reg .f32 %f<7>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_maxnum_unsafe_param_2];
-; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_maxnum_unsafe_param_0];
-; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
-; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
-; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
-; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
-; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
-; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
-; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
-; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
-; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
-; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
-; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
-; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
-; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
-; CHECK-SM70-NEXT: ret;
- %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
- %2 = call bfloat @llvm.maxnum.bf16(bfloat %1, bfloat 0.0)
- ret bfloat %2
-}
-
-define bfloat @fma_bf16_expanded_safe(bfloat %a, bfloat %b, bfloat %c) {
-; CHECK-LABEL: fma_bf16_expanded_safe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<6>;
-; CHECK-NEXT: .reg .b32 %r<9>;
-; CHECK-NEXT: .reg .f32 %f<7>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
-; CHECK-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-NEXT: mov.b32 %f1, %r2;
-; CHECK-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
-; CHECK-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-NEXT: mov.b32 %f2, %r4;
-; CHECK-NEXT: mul.rn.f32 %f3, %f2, %f1;
-; CHECK-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
-; CHECK-NEXT: cvt.u32.u16 %r5, %rs1;
-; CHECK-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-NEXT: mov.b32 %f4, %r6;
-; CHECK-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
-; CHECK-NEXT: shl.b32 %r8, %r7, 16;
-; CHECK-NEXT: mov.b32 %f5, %r8;
-; CHECK-NEXT: add.rn.f32 %f6, %f4, %f5;
-; CHECK-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
-; CHECK-NEXT: mov.b16 %rs4, 0x0000;
-; CHECK-NEXT: max.bf16 %rs5, %rs3, %rs4;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_bf16_expanded_safe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<6>;
-; CHECK-FTZ-NEXT: .reg .b32 %r<9>;
-; CHECK-FTZ-NEXT: .reg .f32 %f<7>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
-; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
-; CHECK-FTZ-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
-; CHECK-FTZ-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f2, %r4;
-; CHECK-FTZ-NEXT: mul.rn.ftz.f32 %f3, %f2, %f1;
-; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs1;
-; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f4, %r6;
-; CHECK-FTZ-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
-; CHECK-FTZ-NEXT: shl.b32 %r8, %r7, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f5, %r8;
-; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f6, %f4, %f5;
-; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
-; CHECK-FTZ-NEXT: mov.b16 %rs4, 0x0000;
-; CHECK-FTZ-NEXT: max.bf16 %rs5, %rs3, %rs4;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_expanded_safe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<6>;
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b32 %r<9>;
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .f32 %f<7>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b32 %f1, %r2;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b32 %f2, %r4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: mul.rn.f32 %f3, %f2, %f1;
-; CHECK-NO-FMA-CONTRACTION-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: cvt.u32.u16 %r5, %rs1;
-; CHECK-NO-FMA-CONTRACTION-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b32 %f4, %r6;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: shl.b32 %r8, %r7, 16;
-; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b32 %f5, %r8;
-; CHECK-NO-FMA-CONTRACTION-NEXT: add.rn.f32 %f6, %f4, %f5;
-; CHECK-NO-FMA-CONTRACTION-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
-; CHECK-NO-FMA-CONTRACTION-NEXT: mov.b16 %rs4, 0x0000;
-; CHECK-NO-FMA-CONTRACTION-NEXT: max.bf16 %rs5, %rs3, %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_expanded_safe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<6>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b32 %r<9>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .f32 %f<7>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b32 %f1, %r2;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b32 %f2, %r4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mul.f32 %f3, %f2, %f1;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: cvt.u32.u16 %r5, %rs1;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b32 %f4, %r6;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: shl.b32 %r8, %r7, 16;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b32 %f5, %r8;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: add.f32 %f6, %f4, %f5;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: mov.b16 %rs4, 0x0000;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: max.bf16 %rs5, %rs3, %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_bf16_expanded_safe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .pred %p<4>;
-; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM70-NEXT: .reg .b32 %r<27>;
-; CHECK-SM70-NEXT: .reg .f32 %f<9>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
-; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
-; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: mul.rn.f32 %f3, %f2, %f1;
-; CHECK-SM70-NEXT: mov.b32 %r5, %f3;
-; CHECK-SM70-NEXT: bfe.u32 %r6, %r5, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r7, %r6, %r5;
-; CHECK-SM70-NEXT: add.s32 %r8, %r7, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f3, %f3;
-; CHECK-SM70-NEXT: or.b32 %r9, %r5, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r10, %r9, %r8, %p1;
-; CHECK-SM70-NEXT: and.b32 %r11, %r10, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f4, %r11;
-; CHECK-SM70-NEXT: ld.param.u16 %r12, [fma_bf16_expanded_safe_param_2];
-; CHECK-SM70-NEXT: shl.b32 %r13, %r12, 16;
-; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
-; CHECK-SM70-NEXT: add.rn.f32 %f6, %f4, %f5;
-; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
-; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
-; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
-; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
-; CHECK-SM70-NEXT: and.b32 %r20, %r19, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f7, %r20;
-; CHECK-SM70-NEXT: max.f32 %f8, %f7, 0f00000000;
-; CHECK-SM70-NEXT: mov.b32 %r21, %f8;
-; CHECK-SM70-NEXT: bfe.u32 %r22, %r21, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r23, %r22, %r21;
-; CHECK-SM70-NEXT: add.s32 %r24, %r23, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f8, %f8;
-; CHECK-SM70-NEXT: or.b32 %r25, %r21, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r26, %r25, %r24, %p3;
-; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r26; }
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
-; CHECK-SM70-NEXT: ret;
- %1 = fmul bfloat %a, %b
- %2 = fadd bfloat %1, %c
- %3 = fcmp ogt bfloat %2, 0.0
- %4 = select i1 %3, bfloat %2, bfloat 0.0
- ret bfloat %4
-}
-
-define bfloat @fma_bf16_expanded_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_expanded_unsafe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
-; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_bf16_expanded_unsafe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.relu.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_expanded_unsafe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_expanded_unsafe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_bf16_expanded_unsafe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .pred %p<3>;
-; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM70-NEXT: .reg .b32 %r<20>;
-; CHECK-SM70-NEXT: .reg .f32 %f<7>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_unsafe_param_2];
-; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_unsafe_param_1];
-; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_unsafe_param_0];
-; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
-; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
-; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
-; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
-; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
-; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
-; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
-; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
-; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
-; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
-; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
-; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
-; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
-; CHECK-SM70-NEXT: ret;
- %1 = fmul bfloat %a, %b
- %2 = fadd bfloat %1, %c
- %3 = fcmp ogt bfloat %2, 0.0
- %4 = select i1 %3, bfloat %2, bfloat 0.0
- ret bfloat %4
-}
-
-define bfloat @fma_bf16_expanded_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_expanded_maxnum_unsafe(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
-; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NEXT: ret;
-;
-; CHECK-FTZ-LABEL: fma_bf16_expanded_maxnum_unsafe(
-; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
-; CHECK-FTZ-EMPTY:
-; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.relu.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FTZ-NEXT: ret;
-;
-; CHECK-NO-FMA-CONTRACTION-LABEL: fma_bf16_expanded_maxnum_unsafe(
-; CHECK-NO-FMA-CONTRACTION: {
-; CHECK-NO-FMA-CONTRACTION-NEXT: .reg .b16 %rs<5>;
-; CHECK-NO-FMA-CONTRACTION-EMPTY:
-; CHECK-NO-FMA-CONTRACTION-NEXT: // %bb.0:
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
-; CHECK-NO-FMA-CONTRACTION-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
-; CHECK-NO-FMA-CONTRACTION-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-NO-FMA-CONTRACTION-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-NO-FMA-CONTRACTION-NEXT: ret;
-;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-LABEL: fma_bf16_expanded_maxnum_unsafe(
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH: {
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: .reg .b16 %rs<5>;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-EMPTY:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: // %bb.0:
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: st.param.b16 [func_retval0], %rs4;
-; CHECK-FMA-CONTRACTION-WITHOUT-UNSAFE-MATH-NEXT: ret;
-;
-; CHECK-SM70-LABEL: fma_bf16_expanded_maxnum_unsafe(
-; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .pred %p<3>;
-; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM70-NEXT: .reg .b32 %r<20>;
-; CHECK-SM70-NEXT: .reg .f32 %f<7>;
-; CHECK-SM70-EMPTY:
-; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_maxnum_unsafe_param_2];
-; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_maxnum_unsafe_param_0];
-; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
-; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
-; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
-; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
-; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
-; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
-; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
-; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
-; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
-; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
-; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
-; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
-; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
-; CHECK-SM70-NEXT: ret;
- %1 = fmul bfloat %a, %b
- %2 = fadd bfloat %1, %c
- %3 = call bfloat @llvm.maxnum.bf16(bfloat %2, bfloat 0.0)
- ret bfloat %3
-}
-
-attributes #0 = { "unsafe-fp-math"="true" }
>From 033a9bde29fa04d96f3571b284423ad5978b5f03 Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Thu, 7 Nov 2024 10:47:53 +0000
Subject: [PATCH 03/14] Rename fpimm0 to fpimm_positive_zero
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 5a4fb90aba2a32..d9b1e7540b173e 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3918,7 +3918,7 @@ def atomic_thread_fence_acq_rel_cta :
NVPTXInst<(outs), (ins), "fence.acq_rel.cta;", []>,
Requires<[hasPTX<60>, hasSM<70>]>;
-def fpimm0 : FPImmLeaf<fAny, [{
+def fpimm_positive_zero : FPImmLeaf<fAny, [{
return Imm.isExactlyValue(+0.0);
}]>;
@@ -3946,16 +3946,16 @@ def NVPTX_fma_oneuse : PatFrag<(ops node:$a, node:$b, node:$c),
}]>;
// FTZ variants
-def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
-def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_BF16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
// No FTZ
-def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[allowUnsafeFPMath]>;
-def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm0)),
+def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[allowUnsafeFPMath]>;
>From 2ca364f91aeadd4656afb7e52f3fd65dd5a9eaec Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Thu, 7 Nov 2024 12:14:32 +0000
Subject: [PATCH 04/14] Add support for f16x2, bf16x2 PTX instructions
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 31 +
llvm/test/CodeGen/NVPTX/fma-relu-contract.ll | 822 ++++++++++++++++++
.../CodeGen/NVPTX/fma-relu-fma-intrinsic.ll | 525 +++++++++++
3 files changed, 1378 insertions(+)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index d9b1e7540b173e..ed6e10650f8311 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3922,6 +3922,9 @@ def fpimm_positive_zero : FPImmLeaf<fAny, [{
return Imm.isExactlyValue(+0.0);
}]>;
+def fpimm_positive_zero_v2f16 : PatFrag<(ops), (v2f16 (bitconvert (i32 0)))>;
+def fpimm_positive_zero_v2bf16 : PatFrag<(ops), (v2bf16 (bitconvert (i32 0)))>;
+
def FMARELU_F16 :
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
"fma.rn.relu.f16 \t$dst, $a, $b, $c;", []>,
@@ -3938,6 +3941,22 @@ def FMARELU_BF16_FTZ :
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
"fma.rn.ftz.relu.bf16 \t$dst, $a, $b, $c;", []>,
Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
+def FMARELU_F16X2 :
+ NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
+ "fma.rn.relu.f16x2 \t$dst, $a, $b, $c;", []>,
+ Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
+def FMARELU_BF16X2 :
+ NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
+ "fma.rn.relu.bf16x2 \t$dst, $a, $b, $c;", []>,
+ Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
+def FMARELU_F16X2_FTZ :
+ NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
+ "fma.rn.ftz.relu.f16x2 \t$dst, $a, $b, $c;", []>,
+ Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
+def FMARELU_BF16X2_FTZ :
+ NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
+ "fma.rn.ftz.relu.bf16x2 \t$dst, $a, $b, $c;", []>,
+ Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
// Patterns will only be used if FMA has a single use, in order to mitigate register pressure
def NVPTX_fma_oneuse : PatFrag<(ops node:$a, node:$b, node:$c),
@@ -3952,6 +3971,12 @@ def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:
def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_BF16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
+def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
+ (FMARELU_F16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
+ Requires<[doF32FTZ, allowUnsafeFPMath]>;
+def : Pat<(v2bf16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2bf16)),
+ (FMARELU_BF16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
+ Requires<[doF32FTZ, allowUnsafeFPMath]>;
// No FTZ
def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
@@ -3959,3 +3984,9 @@ def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:
def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[allowUnsafeFPMath]>;
+def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
+ (FMARELU_F16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
+ Requires<[allowUnsafeFPMath]>;
+def : Pat<(v2bf16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2bf16)),
+ (FMARELU_BF16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
+ Requires<[allowUnsafeFPMath]>;
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
index 74d5ae45997e89..d982a3e9b627af 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
@@ -597,4 +597,826 @@ define bfloat @fma_bf16_expanded_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c)
ret bfloat %3
}
+define <2 x half> @fma_f16x2_expanded_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_expanded_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_param_0];
+; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_expanded_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 0;
+; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: selp.b16 %rs3, %rs2, 0x0000, %p2;
+; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1;
+; CHECK-SM70-NEXT: mov.b32 %r6, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul <2 x half> %a, %b
+ %2 = fadd <2 x half> %1, %c
+ %3 = fcmp ogt <2 x half> %2, <half 0.0, half 0.0>
+ %4 = select <2 x i1> %3, <2 x half> %2, <2 x half> <half 0.0, half 0.0>
+ ret <2 x half> %4
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define <2 x half> @fma_f16x2_expanded_unsafe_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<10>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: max.f16x2 %r6, %r4, %r5;
+; CHECK-NEXT: mov.b32 %r7, 1191200512;
+; CHECK-NEXT: add.f16x2 %r8, %r4, %r7;
+; CHECK-NEXT: add.f16x2 %r9, %r6, %r8;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<10>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
+; CHECK-FTZ-NEXT: max.ftz.f16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: mov.b32 %r7, 1191200512;
+; CHECK-FTZ-NEXT: add.ftz.f16x2 %r8, %r4, %r7;
+; CHECK-FTZ-NEXT: add.ftz.f16x2 %r9, %r6, %r8;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<10>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 0;
+; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: selp.b16 %rs3, %rs2, 0x0000, %p2;
+; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1;
+; CHECK-SM70-NEXT: mov.b32 %r6, {%rs4, %rs3};
+; CHECK-SM70-NEXT: mov.b32 %r7, 1191200512;
+; CHECK-SM70-NEXT: add.f16x2 %r8, %r4, %r7;
+; CHECK-SM70-NEXT: add.f16x2 %r9, %r6, %r8;
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul <2 x half> %a, %b
+ %2 = fadd <2 x half> %1, %c
+ %3 = fcmp ogt <2 x half> %2, <half 0.0, half 0.0>
+ %4 = select <2 x i1> %3, <2 x half> %2, <2 x half> <half 0.0, half 0.0>
+ %5 = fadd <2 x half> %2, <half 7.0, half 7.0>
+ %6 = fadd <2 x half> %4, %5
+ ret <2 x half> %6
+}
+
+define <2 x half> @fma_f16x2_expanded_safe(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
+; CHECK-LABEL: fma_f16x2_expanded_safe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_safe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_safe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_safe_param_0];
+; CHECK-NEXT: mul.rn.f16x2 %r4, %r3, %r2;
+; CHECK-NEXT: add.rn.f16x2 %r5, %r4, %r1;
+; CHECK-NEXT: mov.b32 %r6, 0;
+; CHECK-NEXT: max.f16x2 %r7, %r5, %r6;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_safe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<8>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_safe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_safe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_safe_param_0];
+; CHECK-FTZ-NEXT: mul.rn.ftz.f16x2 %r4, %r3, %r2;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16x2 %r5, %r4, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r6, 0;
+; CHECK-FTZ-NEXT: max.ftz.f16x2 %r7, %r5, %r6;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_expanded_safe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<8>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_safe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_safe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_safe_param_0];
+; CHECK-SM70-NEXT: mul.rn.f16x2 %r4, %r3, %r2;
+; CHECK-SM70-NEXT: add.rn.f16x2 %r5, %r4, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r6, 0;
+; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r5, %r6;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r5;
+; CHECK-SM70-NEXT: selp.b16 %rs3, %rs2, 0x0000, %p2;
+; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1;
+; CHECK-SM70-NEXT: mov.b32 %r7, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul <2 x half> %a, %b
+ %2 = fadd <2 x half> %1, %c
+ %3 = fcmp ogt <2 x half> %2, <half 0.0, half 0.0>
+ %4 = select <2 x i1> %3, <2 x half> %2, <2 x half> <half 0.0, half 0.0>
+ ret <2 x half> %4
+}
+
+define <2 x half> @fma_f16x2_expanded_maxnum_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_expanded_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_unsafe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_expanded_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<5>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-SM70-NEXT: max.f32 %f4, %f3, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-SM70-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul <2 x half> %a, %b
+ %2 = fadd <2 x half> %1, %c
+ %3 = call <2 x half> @llvm.maxnum.f16x2(<2 x half> %2, <2 x half> <half 0.0, half 0.0>)
+ ret <2 x half> %3
+}
+
+define <2 x bfloat> @fma_bf16x2_expanded_safe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
+; CHECK-LABEL: fma_bf16x2_expanded_safe(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<19>;
+; CHECK-NEXT: .reg .b32 %r<23>;
+; CHECK-NEXT: .reg .f32 %f<13>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_safe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_safe_param_0];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_safe_param_1];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-NEXT: mov.b32 %f1, %r5;
+; CHECK-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-NEXT: mov.b32 %f2, %r7;
+; CHECK-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs7, %f3;
+; CHECK-NEXT: cvt.u32.u16 %r8, %rs2;
+; CHECK-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-NEXT: mov.b32 %f4, %r9;
+; CHECK-NEXT: cvt.u32.u16 %r10, %rs5;
+; CHECK-NEXT: shl.b32 %r11, %r10, 16;
+; CHECK-NEXT: mov.b32 %f5, %r11;
+; CHECK-NEXT: mul.rn.f32 %f6, %f5, %f4;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs10, %f6;
+; CHECK-NEXT: cvt.u32.u16 %r12, %rs10;
+; CHECK-NEXT: shl.b32 %r13, %r12, 16;
+; CHECK-NEXT: mov.b32 %f7, %r13;
+; CHECK-NEXT: mov.b32 {%rs12, %rs13}, %r1;
+; CHECK-NEXT: cvt.u32.u16 %r14, %rs13;
+; CHECK-NEXT: shl.b32 %r15, %r14, 16;
+; CHECK-NEXT: mov.b32 %f8, %r15;
+; CHECK-NEXT: add.rn.f32 %f9, %f7, %f8;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs15, %f9;
+; CHECK-NEXT: cvt.u32.u16 %r16, %rs7;
+; CHECK-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-NEXT: mov.b32 %f10, %r17;
+; CHECK-NEXT: cvt.u32.u16 %r18, %rs12;
+; CHECK-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-NEXT: mov.b32 %f11, %r19;
+; CHECK-NEXT: add.rn.f32 %f12, %f10, %f11;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs18, %f12;
+; CHECK-NEXT: mov.b32 %r20, {%rs18, %rs15};
+; CHECK-NEXT: mov.b32 %r21, 0;
+; CHECK-NEXT: max.bf16x2 %r22, %r20, %r21;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r22;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_safe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<19>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<23>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<13>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_safe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_safe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_safe_param_1];
+; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-FTZ-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r5;
+; CHECK-FTZ-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f2, %r7;
+; CHECK-FTZ-NEXT: mul.rn.ftz.f32 %f3, %f2, %f1;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs7, %f3;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r8, %rs2;
+; CHECK-FTZ-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f4, %r9;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r10, %rs5;
+; CHECK-FTZ-NEXT: shl.b32 %r11, %r10, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f5, %r11;
+; CHECK-FTZ-NEXT: mul.rn.ftz.f32 %f6, %f5, %f4;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs10, %f6;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r12, %rs10;
+; CHECK-FTZ-NEXT: shl.b32 %r13, %r12, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f7, %r13;
+; CHECK-FTZ-NEXT: mov.b32 {%rs12, %rs13}, %r1;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r14, %rs13;
+; CHECK-FTZ-NEXT: shl.b32 %r15, %r14, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f8, %r15;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f9, %f7, %f8;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs15, %f9;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r16, %rs7;
+; CHECK-FTZ-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f10, %r17;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r18, %rs12;
+; CHECK-FTZ-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f11, %r19;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f12, %f10, %f11;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs18, %f12;
+; CHECK-FTZ-NEXT: mov.b32 %r20, {%rs18, %rs15};
+; CHECK-FTZ-NEXT: mov.b32 %r21, 0;
+; CHECK-FTZ-NEXT: max.bf16x2 %r22, %r20, %r21;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r22;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_safe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<7>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<19>;
+; CHECK-SM70-NEXT: .reg .b32 %r<45>;
+; CHECK-SM70-NEXT: .reg .f32 %f<15>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_safe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_safe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_safe_param_1];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r8, %f3;
+; CHECK-SM70-NEXT: bfe.u32 %r9, %r8, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, %r8;
+; CHECK-SM70-NEXT: add.s32 %r11, %r10, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f3, %f3;
+; CHECK-SM70-NEXT: or.b32 %r12, %r8, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r13, %r12, %r11, %p1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r14, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r15, %r14, 16;
+; CHECK-SM70-NEXT: mov.b32 %f4, %r15;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: mul.rn.f32 %f6, %f5, %f4;
+; CHECK-SM70-NEXT: mov.b32 %r18, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r19, %r18, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r20, %r19, %r18;
+; CHECK-SM70-NEXT: add.s32 %r21, %r20, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r22, %r18, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r23, %r22, %r21, %p2;
+; CHECK-SM70-NEXT: and.b32 %r24, %r23, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r24;
+; CHECK-SM70-NEXT: mov.b32 {%rs9, %rs10}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r25, %rs9;
+; CHECK-SM70-NEXT: shl.b32 %r26, %r25, 16;
+; CHECK-SM70-NEXT: mov.b32 %f8, %r26;
+; CHECK-SM70-NEXT: add.rn.f32 %f9, %f7, %f8;
+; CHECK-SM70-NEXT: mov.b32 %r27, %f9;
+; CHECK-SM70-NEXT: bfe.u32 %r28, %r27, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r29, %r28, %r27;
+; CHECK-SM70-NEXT: add.s32 %r30, %r29, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f9, %f9;
+; CHECK-SM70-NEXT: or.b32 %r31, %r27, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r32, %r31, %r30, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs12}, %r32; }
+; CHECK-SM70-NEXT: and.b32 %r33, %r13, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f10, %r33;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r34, %rs10;
+; CHECK-SM70-NEXT: shl.b32 %r35, %r34, 16;
+; CHECK-SM70-NEXT: mov.b32 %f11, %r35;
+; CHECK-SM70-NEXT: add.rn.f32 %f12, %f10, %f11;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p4;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r41; }
+; CHECK-SM70-NEXT: and.b32 %r42, %r32, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f13, %r42;
+; CHECK-SM70-NEXT: setp.gt.f32 %p5, %f13, 0f00000000;
+; CHECK-SM70-NEXT: and.b32 %r43, %r41, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f14, %r43;
+; CHECK-SM70-NEXT: setp.gt.f32 %p6, %f14, 0f00000000;
+; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p6;
+; CHECK-SM70-NEXT: selp.b16 %rs18, %rs12, 0x0000, %p5;
+; CHECK-SM70-NEXT: mov.b32 %r44, {%rs18, %rs17};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r44;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul <2 x bfloat> %a, %b
+ %2 = fadd <2 x bfloat> %1, %c
+ %3 = fcmp ogt <2 x bfloat> %2, <bfloat 0.0, bfloat 0.0>
+ %4 = select <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ ret <2 x bfloat> %4
+}
+
+define <2 x bfloat> @fma_bf16x2_expanded_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_expanded_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_param_0];
+; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<19>;
+; CHECK-SM70-NEXT: .reg .b32 %r<31>;
+; CHECK-SM70-NEXT: .reg .f32 %f<11>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r15; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r27; }
+; CHECK-SM70-NEXT: and.b32 %r28, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: setp.gt.f32 %p3, %f9, 0f00000000;
+; CHECK-SM70-NEXT: and.b32 %r29, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f10, %r29;
+; CHECK-SM70-NEXT: setp.gt.f32 %p4, %f10, 0f00000000;
+; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p4;
+; CHECK-SM70-NEXT: selp.b16 %rs18, %rs10, 0x0000, %p3;
+; CHECK-SM70-NEXT: mov.b32 %r30, {%rs18, %rs17};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r30;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul <2 x bfloat> %a, %b
+ %2 = fadd <2 x bfloat> %1, %c
+ %3 = fcmp ogt <2 x bfloat> %2, <bfloat 0.0, bfloat 0.0>
+ %4 = select <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ ret <2 x bfloat> %4
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define <2 x bfloat> @fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<15>;
+; CHECK-NEXT: .reg .b32 %r<20>;
+; CHECK-NEXT: .reg .f32 %f<11>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: max.bf16x2 %r6, %r4, %r5;
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-NEXT: cvt.u32.u16 %r7, %rs1;
+; CHECK-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-NEXT: mov.b32 %f1, %r8;
+; CHECK-NEXT: add.f32 %f2, %f1, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs4, %f2;
+; CHECK-NEXT: cvt.u32.u16 %r9, %rs2;
+; CHECK-NEXT: shl.b32 %r10, %r9, 16;
+; CHECK-NEXT: mov.b32 %f3, %r10;
+; CHECK-NEXT: add.f32 %f4, %f3, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs6, %f4;
+; CHECK-NEXT: mov.b32 {%rs7, %rs8}, %r6;
+; CHECK-NEXT: cvt.u32.u16 %r11, %rs8;
+; CHECK-NEXT: shl.b32 %r12, %r11, 16;
+; CHECK-NEXT: mov.b32 %f5, %r12;
+; CHECK-NEXT: cvt.u32.u16 %r13, %rs6;
+; CHECK-NEXT: shl.b32 %r14, %r13, 16;
+; CHECK-NEXT: mov.b32 %f6, %r14;
+; CHECK-NEXT: add.f32 %f7, %f5, %f6;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs11, %f7;
+; CHECK-NEXT: cvt.u32.u16 %r15, %rs7;
+; CHECK-NEXT: shl.b32 %r16, %r15, 16;
+; CHECK-NEXT: mov.b32 %f8, %r16;
+; CHECK-NEXT: cvt.u32.u16 %r17, %rs4;
+; CHECK-NEXT: shl.b32 %r18, %r17, 16;
+; CHECK-NEXT: mov.b32 %f9, %r18;
+; CHECK-NEXT: add.f32 %f10, %f8, %f9;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs14, %f10;
+; CHECK-NEXT: mov.b32 %r19, {%rs14, %rs11};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r19;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<15>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<20>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<11>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
+; CHECK-FTZ-NEXT: max.bf16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r7, %rs1;
+; CHECK-FTZ-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r8;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f2, %f1, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs4, %f2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r9, %rs2;
+; CHECK-FTZ-NEXT: shl.b32 %r10, %r9, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f3, %r10;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f4, %f3, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs6, %f4;
+; CHECK-FTZ-NEXT: mov.b32 {%rs7, %rs8}, %r6;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r11, %rs8;
+; CHECK-FTZ-NEXT: shl.b32 %r12, %r11, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f5, %r12;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r13, %rs6;
+; CHECK-FTZ-NEXT: shl.b32 %r14, %r13, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f6, %r14;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f7, %f5, %f6;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs11, %f7;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r15, %rs7;
+; CHECK-FTZ-NEXT: shl.b32 %r16, %r15, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f8, %r16;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r17, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r18, %r17, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f9, %r18;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f10, %f8, %f9;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs14, %f10;
+; CHECK-FTZ-NEXT: mov.b32 %r19, {%rs14, %rs11};
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r19;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<9>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<25>;
+; CHECK-SM70-NEXT: .reg .b32 %r<61>;
+; CHECK-SM70-NEXT: .reg .f32 %f<19>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r15; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r27; }
+; CHECK-SM70-NEXT: and.b32 %r28, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: setp.gt.f32 %p3, %f9, 0f00000000;
+; CHECK-SM70-NEXT: and.b32 %r29, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f10, %r29;
+; CHECK-SM70-NEXT: setp.gt.f32 %p4, %f10, 0f00000000;
+; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p4;
+; CHECK-SM70-NEXT: selp.b16 %rs18, %rs10, 0x0000, %p3;
+; CHECK-SM70-NEXT: add.f32 %f11, %f10, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r30, %f11;
+; CHECK-SM70-NEXT: bfe.u32 %r31, %r30, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r32, %r31, %r30;
+; CHECK-SM70-NEXT: add.s32 %r33, %r32, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p5, %f11, %f11;
+; CHECK-SM70-NEXT: or.b32 %r34, %r30, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r35, %r34, %r33, %p5;
+; CHECK-SM70-NEXT: add.f32 %f12, %f9, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p6, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p6;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r42, %rs18;
+; CHECK-SM70-NEXT: shl.b32 %r43, %r42, 16;
+; CHECK-SM70-NEXT: mov.b32 %f13, %r43;
+; CHECK-SM70-NEXT: and.b32 %r44, %r41, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f14, %r44;
+; CHECK-SM70-NEXT: add.f32 %f15, %f13, %f14;
+; CHECK-SM70-NEXT: mov.b32 %r45, %f15;
+; CHECK-SM70-NEXT: bfe.u32 %r46, %r45, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r47, %r46, %r45;
+; CHECK-SM70-NEXT: add.s32 %r48, %r47, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p7, %f15, %f15;
+; CHECK-SM70-NEXT: or.b32 %r49, %r45, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r50, %r49, %r48, %p7;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs20}, %r50; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r51, %rs17;
+; CHECK-SM70-NEXT: shl.b32 %r52, %r51, 16;
+; CHECK-SM70-NEXT: mov.b32 %f16, %r52;
+; CHECK-SM70-NEXT: and.b32 %r53, %r35, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f17, %r53;
+; CHECK-SM70-NEXT: add.f32 %f18, %f16, %f17;
+; CHECK-SM70-NEXT: mov.b32 %r54, %f18;
+; CHECK-SM70-NEXT: bfe.u32 %r55, %r54, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r56, %r55, %r54;
+; CHECK-SM70-NEXT: add.s32 %r57, %r56, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p8, %f18, %f18;
+; CHECK-SM70-NEXT: or.b32 %r58, %r54, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r59, %r58, %r57, %p8;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs23}, %r59; }
+; CHECK-SM70-NEXT: mov.b32 %r60, {%rs23, %rs20};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r60;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul <2 x bfloat> %a, %b
+ %2 = fadd <2 x bfloat> %1, %c
+ %3 = fcmp ogt <2 x bfloat> %2, <bfloat 0.0, bfloat 0.0>
+ %4 = select <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ %5 = fadd <2 x bfloat> %2, <bfloat 7.0, bfloat 7.0>
+ %6 = fadd <2 x bfloat> %4, %5
+ ret <2 x bfloat> %6
+}
+
+define <2 x bfloat> @fma_bf16x2_expanded_maxnum_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_expanded_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_unsafe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
+; CHECK-SM70-NEXT: .reg .b32 %r<43>;
+; CHECK-SM70-NEXT: .reg .f32 %f<13>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: and.b32 %r28, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: max.f32 %f10, %f9, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r29, %f10;
+; CHECK-SM70-NEXT: bfe.u32 %r30, %r29, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r31, %r30, %r29;
+; CHECK-SM70-NEXT: add.s32 %r32, %r31, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f10, %f10;
+; CHECK-SM70-NEXT: or.b32 %r33, %r29, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r34, %r33, %r32, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs13}, %r34; }
+; CHECK-SM70-NEXT: and.b32 %r35, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f11, %r35;
+; CHECK-SM70-NEXT: max.f32 %f12, %f11, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p4;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r41; }
+; CHECK-SM70-NEXT: mov.b32 %r42, {%rs15, %rs13};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r42;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul <2 x bfloat> %a, %b
+ %2 = fadd <2 x bfloat> %1, %c
+ %3 = call <2 x bfloat> @llvm.maxnum.bf16x2(<2 x bfloat> %2, <2 x bfloat> <bfloat 0.0, bfloat 0.0>)
+ ret <2 x bfloat> %3
+}
+
attributes #0 = { "unsafe-fp-math"="true" }
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
index 3e114e02d463b0..22cd1f2dbe973c 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
@@ -397,4 +397,529 @@ define bfloat @fma_bf16_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
ret bfloat %2
}
+define <2 x half> @fma_f16x2_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_param_0];
+; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 0;
+; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: selp.b16 %rs3, %rs2, 0x0000, %p2;
+; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1;
+; CHECK-SM70-NEXT: mov.b32 %r6, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-SM70-NEXT: ret;
+ %1 = call <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c)
+ %2 = fcmp ogt <2 x half> %1, <half 0.0, half 0.0>
+ %3 = select <2 x i1> %2, <2 x half> %1, <2 x half> <half 0.0, half 0.0>
+ ret <2 x half> %3
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define <2 x half> @fma_f16x2_unsafe_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_unsafe_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 1191200512;
+; CHECK-NEXT: add.f16x2 %r6, %r4, %r5;
+; CHECK-NEXT: add.f16x2 %r7, %r6, %r4;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<8>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 1191200512;
+; CHECK-FTZ-NEXT: add.ftz.f16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: add.ftz.f16x2 %r7, %r6, %r4;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_unsafe_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b32 %r<8>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 1191200512;
+; CHECK-SM70-NEXT: add.f16x2 %r6, %r4, %r5;
+; CHECK-SM70-NEXT: add.f16x2 %r7, %r6, %r4;
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-SM70-NEXT: ret;
+ %1 = call <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c)
+ %2 = fcmp ogt <2 x half> %1, <half 0.0, half 0.0>
+ %3 = select <2 x i1> %2, <2 x half> %1, <2 x half> <half 0.0, half 0.0>
+ %4 = fadd <2 x half> %1, <half 7.0, half 7.0>
+ %5 = fadd <2 x half> %4, %1
+ ret <2 x half> %5
+}
+
+define <2 x half> @fma_f16x2_maxnum_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_unsafe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_unsafe_param_0];
+; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<5>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-SM70-NEXT: max.f32 %f4, %f3, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-SM70-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-SM70-NEXT: ret;
+ %1 = call <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c)
+ %2 = call <2 x half> @llvm.maxnum.f16x2(<2 x half> %1, <2 x half> <half 0.0, half 0.0>)
+ ret <2 x half> %2
+}
+
+define <2 x bfloat> @fma_bf16x2_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_param_0];
+; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<19>;
+; CHECK-SM70-NEXT: .reg .b32 %r<31>;
+; CHECK-SM70-NEXT: .reg .f32 %f<11>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r15; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r27; }
+; CHECK-SM70-NEXT: and.b32 %r28, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: setp.gt.f32 %p3, %f9, 0f00000000;
+; CHECK-SM70-NEXT: and.b32 %r29, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f10, %r29;
+; CHECK-SM70-NEXT: setp.gt.f32 %p4, %f10, 0f00000000;
+; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p4;
+; CHECK-SM70-NEXT: selp.b16 %rs18, %rs10, 0x0000, %p3;
+; CHECK-SM70-NEXT: mov.b32 %r30, {%rs18, %rs17};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r30;
+; CHECK-SM70-NEXT: ret;
+ %1 = call <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
+ %2 = fcmp ogt <2 x bfloat> %1, <bfloat 0.0, bfloat 0.0>
+ %3 = select <2 x i1> %2, <2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ ret <2 x bfloat> %3
+}
+
+; FMA_relu shouldn't be selected if the FMA operation has multiple uses
+define <2 x bfloat> @fma_bf16x2_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_unsafe_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<11>;
+; CHECK-NEXT: .reg .b32 %r<14>;
+; CHECK-NEXT: .reg .f32 %f<9>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-NEXT: mov.b32 %f1, %r6;
+; CHECK-NEXT: add.f32 %f2, %f1, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs4, %f2;
+; CHECK-NEXT: cvt.u32.u16 %r7, %rs2;
+; CHECK-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-NEXT: mov.b32 %f3, %r8;
+; CHECK-NEXT: add.f32 %f4, %f3, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs6, %f4;
+; CHECK-NEXT: cvt.u32.u16 %r9, %rs6;
+; CHECK-NEXT: shl.b32 %r10, %r9, 16;
+; CHECK-NEXT: mov.b32 %f5, %r10;
+; CHECK-NEXT: add.f32 %f6, %f5, %f3;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs8, %f6;
+; CHECK-NEXT: cvt.u32.u16 %r11, %rs4;
+; CHECK-NEXT: shl.b32 %r12, %r11, 16;
+; CHECK-NEXT: mov.b32 %f7, %r12;
+; CHECK-NEXT: add.f32 %f8, %f7, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs10, %f8;
+; CHECK-NEXT: mov.b32 %r13, {%rs10, %rs8};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<11>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<14>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<9>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r6;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f2, %f1, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs4, %f2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r7, %rs2;
+; CHECK-FTZ-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f3, %r8;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f4, %f3, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs6, %f4;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r9, %rs6;
+; CHECK-FTZ-NEXT: shl.b32 %r10, %r9, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f5, %r10;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f6, %f5, %f3;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs8, %f6;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r11, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r12, %r11, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f7, %r12;
+; CHECK-FTZ-NEXT: add.ftz.f32 %f8, %f7, %f1;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs10, %f8;
+; CHECK-FTZ-NEXT: mov.b32 %r13, {%rs10, %rs8};
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_unsafe_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<7>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
+; CHECK-SM70-NEXT: .reg .b32 %r<57>;
+; CHECK-SM70-NEXT: .reg .f32 %f<17>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: and.b32 %r28, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: add.f32 %f10, %f9, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r29, %f10;
+; CHECK-SM70-NEXT: bfe.u32 %r30, %r29, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r31, %r30, %r29;
+; CHECK-SM70-NEXT: add.s32 %r32, %r31, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f10, %f10;
+; CHECK-SM70-NEXT: or.b32 %r33, %r29, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r34, %r33, %r32, %p3;
+; CHECK-SM70-NEXT: and.b32 %r35, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f11, %r35;
+; CHECK-SM70-NEXT: add.f32 %f12, %f11, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p4;
+; CHECK-SM70-NEXT: and.b32 %r42, %r41, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f13, %r42;
+; CHECK-SM70-NEXT: add.f32 %f14, %f13, %f11;
+; CHECK-SM70-NEXT: mov.b32 %r43, %f14;
+; CHECK-SM70-NEXT: bfe.u32 %r44, %r43, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r45, %r44, %r43;
+; CHECK-SM70-NEXT: add.s32 %r46, %r45, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p5, %f14, %f14;
+; CHECK-SM70-NEXT: or.b32 %r47, %r43, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r48, %r47, %r46, %p5;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs13}, %r48; }
+; CHECK-SM70-NEXT: and.b32 %r49, %r34, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f15, %r49;
+; CHECK-SM70-NEXT: add.f32 %f16, %f15, %f9;
+; CHECK-SM70-NEXT: mov.b32 %r50, %f16;
+; CHECK-SM70-NEXT: bfe.u32 %r51, %r50, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r52, %r51, %r50;
+; CHECK-SM70-NEXT: add.s32 %r53, %r52, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p6, %f16, %f16;
+; CHECK-SM70-NEXT: or.b32 %r54, %r50, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r55, %r54, %r53, %p6;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r55; }
+; CHECK-SM70-NEXT: mov.b32 %r56, {%rs15, %rs13};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r56;
+; CHECK-SM70-NEXT: ret;
+ %1 = call <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
+ %2 = fcmp ogt <2 x bfloat> %1, <bfloat 0.0, bfloat 0.0>
+ %3 = select <2 x i1> %2, <2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ %4 = fadd <2 x bfloat> %1, <bfloat 7.0, bfloat 7.0>
+ %5 = fadd <2 x bfloat> %4, %1
+ ret <2 x bfloat> %5
+}
+
+define <2 x bfloat> @fma_bf16x2_maxnum_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_maxnum_unsafe(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_unsafe_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_unsafe_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_unsafe_param_0];
+; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_maxnum_unsafe(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_unsafe_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_maxnum_unsafe(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
+; CHECK-SM70-NEXT: .reg .b32 %r<43>;
+; CHECK-SM70-NEXT: .reg .f32 %f<13>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: and.b32 %r28, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: max.f32 %f10, %f9, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r29, %f10;
+; CHECK-SM70-NEXT: bfe.u32 %r30, %r29, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r31, %r30, %r29;
+; CHECK-SM70-NEXT: add.s32 %r32, %r31, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f10, %f10;
+; CHECK-SM70-NEXT: or.b32 %r33, %r29, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r34, %r33, %r32, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs13}, %r34; }
+; CHECK-SM70-NEXT: and.b32 %r35, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f11, %r35;
+; CHECK-SM70-NEXT: max.f32 %f12, %f11, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p4;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r41; }
+; CHECK-SM70-NEXT: mov.b32 %r42, {%rs15, %rs13};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r42;
+; CHECK-SM70-NEXT: ret;
+ %1 = call <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
+ %2 = call <2 x bfloat> @llvm.maxnum.bf16x2(<2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0>)
+ ret <2 x bfloat> %2
+}
+
attributes #0 = { "unsafe-fp-math"="true" }
>From 340e0bbc8234e6c53930d48e1ad9138991c34f2e Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Thu, 7 Nov 2024 14:32:45 +0000
Subject: [PATCH 05/14] Remove support for fma.rn.ftz{.relu}.bf16
The PTX ISA docs note that FTZ is not permitted for FTZ for bf16 types.
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 51 +++++--------------
llvm/test/CodeGen/NVPTX/fma-relu-contract.ll | 12 ++---
.../CodeGen/NVPTX/fma-relu-fma-intrinsic.ll | 12 ++---
3 files changed, 24 insertions(+), 51 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index ed6e10650f8311..99a25e8941f7bc 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -418,12 +418,6 @@ multiclass F3_fma_component<string OpcStr, SDNode OpNode> {
!strconcat(OpcStr, ".f16x2 \t$dst, $a, $b;"),
[(set Int32Regs:$dst, (OpNode (v2f16 Int32Regs:$a), (v2f16 Int32Regs:$b)))]>,
Requires<[useFP16Math, allowFMA]>;
- def bf16rr_ftz :
- NVPTXInst<(outs Int16Regs:$dst),
- (ins Int16Regs:$a, Int16Regs:$b),
- !strconcat(OpcStr, ".ftz.bf16 \t$dst, $a, $b;"),
- [(set Int16Regs:$dst, (OpNode (bf16 Int16Regs:$a), (bf16 Int16Regs:$b)))]>,
- Requires<[hasBF16Math, allowFMA, doF32FTZ]>;
def bf16rr :
NVPTXInst<(outs Int16Regs:$dst),
(ins Int16Regs:$a, Int16Regs:$b),
@@ -431,12 +425,6 @@ multiclass F3_fma_component<string OpcStr, SDNode OpNode> {
[(set Int16Regs:$dst, (OpNode (bf16 Int16Regs:$a), (bf16 Int16Regs:$b)))]>,
Requires<[hasBF16Math, allowFMA]>;
- def bf16x2rr_ftz :
- NVPTXInst<(outs Int32Regs:$dst),
- (ins Int32Regs:$a, Int32Regs:$b),
- !strconcat(OpcStr, ".ftz.bf16x2 \t$dst, $a, $b;"),
- [(set (v2bf16 Int32Regs:$dst), (OpNode (v2bf16 Int32Regs:$a), (v2bf16 Int32Regs:$b)))]>,
- Requires<[hasBF16Math, allowFMA, doF32FTZ]>;
def bf16x2rr :
NVPTXInst<(outs Int32Regs:$dst),
(ins Int32Regs:$a, Int32Regs:$b),
@@ -1423,9 +1411,7 @@ defm FMA16_ftz : FMA_F16<"fma.rn.ftz.f16", f16, Int16Regs, doF32FTZ>;
defm FMA16 : FMA_F16<"fma.rn.f16", f16, Int16Regs, True>;
defm FMA16x2_ftz : FMA_F16<"fma.rn.ftz.f16x2", v2f16, Int32Regs, doF32FTZ>;
defm FMA16x2 : FMA_F16<"fma.rn.f16x2", v2f16, Int32Regs, True>;
-defm BFMA16_ftz : FMA_BF16<"fma.rn.ftz.bf16", bf16, Int16Regs, doF32FTZ>;
defm BFMA16 : FMA_BF16<"fma.rn.bf16", bf16, Int16Regs, True>;
-defm BFMA16x2_ftz : FMA_BF16<"fma.rn.ftz.bf16x2", v2bf16, Int32Regs, doF32FTZ>;
defm BFMA16x2 : FMA_BF16<"fma.rn.bf16x2", v2bf16, Int32Regs, True>;
defm FMA32_ftz : FMA<"fma.rn.ftz.f32", Float32Regs, f32imm, doF32FTZ>;
defm FMA32 : FMA<"fma.rn.f32", Float32Regs, f32imm, True>;
@@ -3925,6 +3911,12 @@ def fpimm_positive_zero : FPImmLeaf<fAny, [{
def fpimm_positive_zero_v2f16 : PatFrag<(ops), (v2f16 (bitconvert (i32 0)))>;
def fpimm_positive_zero_v2bf16 : PatFrag<(ops), (v2bf16 (bitconvert (i32 0)))>;
+// Patterns will only be used if FMA has a single use, in order to mitigate register pressure
+def NVPTX_fma_oneuse : PatFrag<(ops node:$a, node:$b, node:$c),
+ (fma node:$a, node:$b, node:$c), [{
+ return N->hasOneUse();
+}]>;
+
def FMARELU_F16 :
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
"fma.rn.relu.f16 \t$dst, $a, $b, $c;", []>,
@@ -3933,14 +3925,6 @@ def FMARELU_BF16 :
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
"fma.rn.relu.bf16 \t$dst, $a, $b, $c;", []>,
Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
-def FMARELU_F16_FTZ :
- NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
- "fma.rn.ftz.relu.f16 \t$dst, $a, $b, $c;", []>,
- Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
-def FMARELU_BF16_FTZ :
- NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
- "fma.rn.ftz.relu.bf16 \t$dst, $a, $b, $c;", []>,
- Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
def FMARELU_F16X2 :
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
"fma.rn.relu.f16x2 \t$dst, $a, $b, $c;", []>,
@@ -3949,34 +3933,23 @@ def FMARELU_BF16X2 :
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
"fma.rn.relu.bf16x2 \t$dst, $a, $b, $c;", []>,
Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
+// FTZ variants are only supported by fp16, not bf16
+def FMARELU_F16_FTZ :
+ NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
+ "fma.rn.ftz.relu.f16 \t$dst, $a, $b, $c;", []>,
+ Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
def FMARELU_F16X2_FTZ :
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
"fma.rn.ftz.relu.f16x2 \t$dst, $a, $b, $c;", []>,
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
-def FMARELU_BF16X2_FTZ :
- NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
- "fma.rn.ftz.relu.bf16x2 \t$dst, $a, $b, $c;", []>,
- Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
-
-// Patterns will only be used if FMA has a single use, in order to mitigate register pressure
-def NVPTX_fma_oneuse : PatFrag<(ops node:$a, node:$b, node:$c),
- (fma node:$a, node:$b, node:$c), [{
- return N->hasOneUse();
-}]>;
-// FTZ variants
+// FTZ variants are only supported by fp16, not bf16
def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
-def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
- (FMARELU_BF16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
- Requires<[doF32FTZ, allowUnsafeFPMath]>;
def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
(FMARELU_F16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
Requires<[doF32FTZ, allowUnsafeFPMath]>;
-def : Pat<(v2bf16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2bf16)),
- (FMARELU_BF16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
- Requires<[doF32FTZ, allowUnsafeFPMath]>;
// No FTZ
def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
index d982a3e9b627af..4afec8f93c6f06 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
@@ -352,7 +352,7 @@ define bfloat @fma_bf16_expanded_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
@@ -442,7 +442,7 @@ define bfloat @fma_bf16_expanded_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %
; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_0];
; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_1];
; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-FTZ-NEXT: fma.rn.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
; CHECK-FTZ-NEXT: max.bf16 %rs6, %rs4, %rs5;
; CHECK-FTZ-NEXT: cvt.u32.u16 %r1, %rs4;
@@ -549,7 +549,7 @@ define bfloat @fma_bf16_expanded_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c)
; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
@@ -1037,7 +1037,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe(<2 x bfloat> %a, <2 x bfloat> %b
; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_param_2];
; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_param_1];
; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_param_0];
-; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
@@ -1166,7 +1166,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(<2 x bfloat
; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-FTZ-NEXT: fma.rn.ftz.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
; CHECK-FTZ-NEXT: max.bf16x2 %r6, %r4, %r5;
; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r4;
@@ -1336,7 +1336,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_maxnum_unsafe(<2 x bfloat> %a, <2 x bfl
; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_unsafe_param_2];
; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_unsafe_param_1];
; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
index 22cd1f2dbe973c..95a5c92fe328e5 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
@@ -175,7 +175,7 @@ define bfloat @fma_bf16_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
@@ -259,7 +259,7 @@ define bfloat @fma_bf16_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat
; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_multiple_uses_of_fma_param_0];
; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_multiple_uses_of_fma_param_1];
; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-FTZ-NEXT: fma.rn.ftz.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: cvt.u32.u16 %r1, %rs4;
; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
@@ -350,7 +350,7 @@ define bfloat @fma_bf16_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
@@ -573,7 +573,7 @@ define <2 x bfloat> @fma_bf16x2_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bf
; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_param_2];
; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_param_1];
; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_param_0];
-; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
@@ -692,7 +692,7 @@ define <2 x bfloat> @fma_bf16x2_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2
; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_2];
; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_1];
; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-FTZ-NEXT: fma.rn.ftz.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r4;
; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs1;
; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
@@ -840,7 +840,7 @@ define <2 x bfloat> @fma_bf16x2_maxnum_unsafe(<2 x bfloat> %a, <2 x bfloat> %b,
; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_unsafe_param_2];
; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_unsafe_param_1];
; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: fma.rn.ftz.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
>From 280184e6706ba1390244d61dc24c67ccf482554b Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Thu, 7 Nov 2024 15:20:17 +0000
Subject: [PATCH 06/14] Update comment
fma.ftz isn't supported for bf16.
---
llvm/test/CodeGen/NVPTX/fma-relu-contract.ll | 2 +-
llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
index 4afec8f93c6f06..79afbe30382eb9 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 | FileCheck %s
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
-; Using FTZ should emit fma.ftz.relu
+; Using FTZ should emit fma.ftz.relu for f16, not for bf16
; RUN: llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK-FTZ
; RUN: %if ptxas %{ llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
index 95a5c92fe328e5..6fdaf9f911e45c 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 | FileCheck %s
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
-; Using FTZ should emit fma.ftz.relu
+; Using FTZ should emit fma.ftz.relu for f16, not for bf16
; RUN: llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK-FTZ
; RUN: %if ptxas %{ llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
>From 4402e254d2abfcb5745fdb8747a0f16347b035f0 Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Fri, 8 Nov 2024 12:52:41 +0000
Subject: [PATCH 07/14] Check for noNaNs instead of unsafeFPMath
The pattern substitution for fmax(fma() 0) is only valid if NaNs cannot
be emitted. This is because fmax is guaranteed to return the non-NaN
arg, whereas fma.relu is NaN preserving.
---
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 5 +
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 1 +
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 10 +
llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 1 +
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 13 +-
llvm/test/CodeGen/NVPTX/fma-relu-contract.ll | 781 ++++++++----------
.../CodeGen/NVPTX/fma-relu-fma-intrinsic.ll | 315 +++----
7 files changed, 504 insertions(+), 622 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 965ed98630a28d..df2bcd71ce71b1 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -85,6 +85,11 @@ bool NVPTXDAGToDAGISel::allowUnsafeFPMath() const {
return TL->allowUnsafeFPMath(*MF);
}
+bool NVPTXDAGToDAGISel::noNaNsFPMath() const {
+ const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
+ return TL->noNaNsFPMath(*MF);
+}
+
bool NVPTXDAGToDAGISel::doRsqrtOpt() const { return EnableRsqrtOpt; }
/// Select - Select instructions not customized! Used for
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index c128c082c29837..0a53c8c3f30b6d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -48,6 +48,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
bool useF32FTZ() const;
bool allowFMA() const;
bool allowUnsafeFPMath() const;
+ bool noNaNsFPMath() const;
bool doRsqrtOpt() const;
NVPTXScopes Scopes{};
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index a95cba586b8fc3..46db3fc289f877 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -5360,6 +5360,16 @@ bool NVPTXTargetLowering::allowUnsafeFPMath(MachineFunction &MF) const {
return F.getFnAttribute("unsafe-fp-math").getValueAsBool();
}
+bool NVPTXTargetLowering::noNaNsFPMath(MachineFunction &MF) const {
+ // Honor TargetOptions flags that explicitly say unsafe math is okay.
+ if (MF.getTarget().Options.NoNaNsFPMath)
+ return true;
+
+ // Allow unsafe math if unsafe-fp-math attribute explicitly says so.
+ const Function &F = MF.getFunction();
+ return F.getFnAttribute("no-nans-fp-math").getValueAsBool();
+}
+
static bool isConstZero(const SDValue &Operand) {
const auto *Const = dyn_cast<ConstantSDNode>(Operand);
return Const && Const->getZExtValue() == 0;
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
index 824a659671967a..5c72e3b3d29cd3 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -576,6 +576,7 @@ class NVPTXTargetLowering : public TargetLowering {
bool allowFMA(MachineFunction &MF, CodeGenOptLevel OptLevel) const;
bool allowUnsafeFPMath(MachineFunction &MF) const;
+ bool noNaNsFPMath(MachineFunction &MF) const;
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
EVT) const override {
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 99a25e8941f7bc..5bd76949960f0c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -152,6 +152,7 @@ def allowFMA : Predicate<"allowFMA()">;
def noFMA : Predicate<"!allowFMA()">;
def allowUnsafeFPMath : Predicate<"allowUnsafeFPMath()">;
def noUnsafeFPMath : Predicate<"!allowUnsafeFPMath()">;
+def noNaNsFPMath : Predicate<"noNaNsFPMath()">;
def do_DIVF32_APPROX : Predicate<"getDivF32Level()==0">;
def do_DIVF32_FULL : Predicate<"getDivF32Level()==1">;
@@ -3946,20 +3947,20 @@ def FMARELU_F16X2_FTZ :
// FTZ variants are only supported by fp16, not bf16
def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
- Requires<[doF32FTZ, allowUnsafeFPMath]>;
+ Requires<[doF32FTZ, noNaNsFPMath]>;
def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
(FMARELU_F16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
- Requires<[doF32FTZ, allowUnsafeFPMath]>;
+ Requires<[doF32FTZ, noNaNsFPMath]>;
// No FTZ
def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
- Requires<[allowUnsafeFPMath]>;
+ Requires<[noNaNsFPMath]>;
def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
(FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
- Requires<[allowUnsafeFPMath]>;
+ Requires<[noNaNsFPMath]>;
def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
(FMARELU_F16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
- Requires<[allowUnsafeFPMath]>;
+ Requires<[noNaNsFPMath]>;
def : Pat<(v2bf16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2bf16)),
(FMARELU_BF16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
- Requires<[allowUnsafeFPMath]>;
+ Requires<[noNaNsFPMath]>;
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
index 79afbe30382eb9..f853872fe68d14 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
@@ -9,40 +9,40 @@
; SM < 80 or (which needs PTX version >= 70) should not emit fma{.ftz}.relu
; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 | FileCheck %s --check-prefixes=CHECK-SM70
-define half @fma_f16_expanded_unsafe(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_expanded_unsafe(
+define half @fma_f16_expanded_no_nans(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_expanded_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_param_2];
; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16_expanded_unsafe(
+; CHECK-FTZ-LABEL: fma_f16_expanded_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_param_2];
; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16_expanded_unsafe(
+; CHECK-SM70-LABEL: fma_f16_expanded_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
; CHECK-SM70-NEXT: .reg .f32 %f<3>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_param_2];
; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
@@ -57,15 +57,15 @@ define half @fma_f16_expanded_unsafe(half %a, half %b, half %c) #0 {
}
; FMA relu shouldn't be selected if the FMA operation has multiple uses
-define half @fma_f16_expanded_unsafe_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_expanded_unsafe_multiple_uses_of_fma(
+define half @fma_f16_expanded_no_nans_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_expanded_no_nans_multiple_uses_of_fma(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<10>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_2];
; CHECK-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: mov.b16 %rs5, 0x0000;
; CHECK-NEXT: max.f16 %rs6, %rs4, %rs5;
@@ -75,14 +75,14 @@ define half @fma_f16_expanded_unsafe_multiple_uses_of_fma(half %a, half %b, half
; CHECK-NEXT: st.param.b16 [func_retval0], %rs9;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ-LABEL: fma_f16_expanded_no_nans_multiple_uses_of_fma(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<10>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_2];
; CHECK-FTZ-NEXT: fma.rn.ftz.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
; CHECK-FTZ-NEXT: max.ftz.f16 %rs6, %rs4, %rs5;
@@ -92,15 +92,15 @@ define half @fma_f16_expanded_unsafe_multiple_uses_of_fma(half %a, half %b, half
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs9;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-SM70-LABEL: fma_f16_expanded_no_nans_multiple_uses_of_fma(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b16 %rs<9>;
; CHECK-SM70-NEXT: .reg .f32 %f<3>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_2];
; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
@@ -119,52 +119,49 @@ define half @fma_f16_expanded_unsafe_multiple_uses_of_fma(half %a, half %b, half
ret half %6
}
-define half @fma_f16_expanded_safe(half %a, half %b, half %c) {
-; CHECK-LABEL: fma_f16_expanded_safe(
+define half @fma_f16_expanded_unsafe_with_nans(half %a, half %b, half %c) #1 {
+; CHECK-LABEL: fma_f16_expanded_unsafe_with_nans(
; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<8>;
+; CHECK-NEXT: .reg .b16 %rs<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
-; CHECK-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
-; CHECK-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
-; CHECK-NEXT: mov.b16 %rs6, 0x0000;
-; CHECK-NEXT: max.f16 %rs7, %rs5, %rs6;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_with_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_with_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_with_nans_param_2];
+; CHECK-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-NEXT: max.f16 %rs6, %rs4, %rs5;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16_expanded_safe(
+; CHECK-FTZ-LABEL: fma_f16_expanded_unsafe_with_nans(
; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<8>;
+; CHECK-FTZ-NEXT: .reg .b16 %rs<7>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
-; CHECK-FTZ-NEXT: mul.rn.ftz.f16 %rs3, %rs1, %rs2;
-; CHECK-FTZ-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
-; CHECK-FTZ-NEXT: add.rn.ftz.f16 %rs5, %rs3, %rs4;
-; CHECK-FTZ-NEXT: mov.b16 %rs6, 0x0000;
-; CHECK-FTZ-NEXT: max.ftz.f16 %rs7, %rs5, %rs6;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_with_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_with_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_with_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-FTZ-NEXT: max.ftz.f16 %rs6, %rs4, %rs5;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16_expanded_safe(
+; CHECK-SM70-LABEL: fma_f16_expanded_unsafe_with_nans(
; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .b16 %rs<7>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
; CHECK-SM70-NEXT: .reg .f32 %f<3>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_safe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_safe_param_1];
-; CHECK-SM70-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
-; CHECK-SM70-NEXT: ld.param.b16 %rs4, [fma_f16_expanded_safe_param_2];
-; CHECK-SM70-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
-; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs5;
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_unsafe_with_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_unsafe_with_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_unsafe_with_nans_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
-; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs6, %f2;
-; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs6;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
; CHECK-SM70-NEXT: ret;
%1 = fmul half %a, %b
%2 = fadd half %1, %c
@@ -173,40 +170,40 @@ define half @fma_f16_expanded_safe(half %a, half %b, half %c) {
ret half %4
}
-define half @fma_f16_expanded_maxnum_unsafe(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_expanded_maxnum_unsafe(
+define half @fma_f16_expanded_maxnum_no_nans(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_expanded_maxnum_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_no_nans_param_2];
; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK-FTZ-LABEL: fma_f16_expanded_maxnum_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_no_nans_param_2];
; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16_expanded_maxnum_unsafe(
+; CHECK-SM70-LABEL: fma_f16_expanded_maxnum_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
; CHECK-SM70-NEXT: .reg .f32 %f<3>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_no_nans_param_2];
; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
@@ -219,91 +216,63 @@ define half @fma_f16_expanded_maxnum_unsafe(half %a, half %b, half %c) #0 {
ret half %3
}
-define bfloat @fma_bf16_expanded_safe(bfloat %a, bfloat %b, bfloat %c) {
-; CHECK-LABEL: fma_bf16_expanded_safe(
+define bfloat @fma_bf16_expanded_unsafe_with_nans(bfloat %a, bfloat %b, bfloat %c) #1 {
+; CHECK-LABEL: fma_bf16_expanded_unsafe_with_nans(
; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<6>;
-; CHECK-NEXT: .reg .b32 %r<9>;
-; CHECK-NEXT: .reg .f32 %f<7>;
+; CHECK-NEXT: .reg .b16 %rs<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
-; CHECK-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-NEXT: mov.b32 %f1, %r2;
-; CHECK-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
-; CHECK-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-NEXT: mov.b32 %f2, %r4;
-; CHECK-NEXT: mul.rn.f32 %f3, %f2, %f1;
-; CHECK-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
-; CHECK-NEXT: cvt.u32.u16 %r5, %rs1;
-; CHECK-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-NEXT: mov.b32 %f4, %r6;
-; CHECK-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
-; CHECK-NEXT: shl.b32 %r8, %r7, 16;
-; CHECK-NEXT: mov.b32 %f5, %r8;
-; CHECK-NEXT: add.rn.f32 %f6, %f4, %f5;
-; CHECK-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
-; CHECK-NEXT: mov.b16 %rs4, 0x0000;
-; CHECK-NEXT: max.bf16 %rs5, %rs3, %rs4;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_with_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_with_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_with_nans_param_2];
+; CHECK-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-NEXT: max.bf16 %rs6, %rs4, %rs5;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16_expanded_safe(
+; CHECK-FTZ-LABEL: fma_bf16_expanded_unsafe_with_nans(
; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<6>;
-; CHECK-FTZ-NEXT: .reg .b32 %r<9>;
-; CHECK-FTZ-NEXT: .reg .f32 %f<7>;
+; CHECK-FTZ-NEXT: .reg .b16 %rs<7>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
-; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
-; CHECK-FTZ-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
-; CHECK-FTZ-NEXT: shl.b32 %r4, %r3, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f2, %r4;
-; CHECK-FTZ-NEXT: mul.rn.ftz.f32 %f3, %f2, %f1;
-; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs1, %f3;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs1;
-; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f4, %r6;
-; CHECK-FTZ-NEXT: ld.param.u16 %r7, [fma_bf16_expanded_safe_param_2];
-; CHECK-FTZ-NEXT: shl.b32 %r8, %r7, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f5, %r8;
-; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f6, %f4, %f5;
-; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs3, %f6;
-; CHECK-FTZ-NEXT: mov.b16 %rs4, 0x0000;
-; CHECK-FTZ-NEXT: max.bf16 %rs5, %rs3, %rs4;
-; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_with_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_with_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_with_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-FTZ-NEXT: max.bf16 %rs6, %rs4, %rs5;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16_expanded_safe(
+; CHECK-SM70-LABEL: fma_bf16_expanded_unsafe_with_nans(
; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .pred %p<4>;
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM70-NEXT: .reg .b32 %r<27>;
-; CHECK-SM70-NEXT: .reg .f32 %f<9>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_safe_param_1];
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_unsafe_with_nans_param_2];
; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_safe_param_0];
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_unsafe_with_nans_param_1];
; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: mul.rn.f32 %f3, %f2, %f1;
-; CHECK-SM70-NEXT: mov.b32 %r5, %f3;
-; CHECK-SM70-NEXT: bfe.u32 %r6, %r5, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r7, %r6, %r5;
-; CHECK-SM70-NEXT: add.s32 %r8, %r7, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f3, %f3;
-; CHECK-SM70-NEXT: or.b32 %r9, %r5, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r10, %r9, %r8, %p1;
-; CHECK-SM70-NEXT: and.b32 %r11, %r10, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f4, %r11;
-; CHECK-SM70-NEXT: ld.param.u16 %r12, [fma_bf16_expanded_safe_param_2];
-; CHECK-SM70-NEXT: shl.b32 %r13, %r12, 16;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_unsafe_with_nans_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
-; CHECK-SM70-NEXT: add.rn.f32 %f6, %f4, %f5;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
@@ -311,17 +280,7 @@ define bfloat @fma_bf16_expanded_safe(bfloat %a, bfloat %b, bfloat %c) {
; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
-; CHECK-SM70-NEXT: and.b32 %r20, %r19, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f7, %r20;
-; CHECK-SM70-NEXT: max.f32 %f8, %f7, 0f00000000;
-; CHECK-SM70-NEXT: mov.b32 %r21, %f8;
-; CHECK-SM70-NEXT: bfe.u32 %r22, %r21, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r23, %r22, %r21;
-; CHECK-SM70-NEXT: add.s32 %r24, %r23, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f8, %f8;
-; CHECK-SM70-NEXT: or.b32 %r25, %r21, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r26, %r25, %r24, %p3;
-; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r26; }
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
; CHECK-SM70-NEXT: ret;
%1 = fmul bfloat %a, %b
@@ -331,32 +290,32 @@ define bfloat @fma_bf16_expanded_safe(bfloat %a, bfloat %b, bfloat %c) {
ret bfloat %4
}
-define bfloat @fma_bf16_expanded_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_expanded_unsafe(
+define bfloat @fma_bf16_expanded_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_expanded_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_no_nans_param_2];
; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16_expanded_unsafe(
+; CHECK-FTZ-LABEL: fma_bf16_expanded_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_no_nans_param_2];
; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16_expanded_unsafe(
+; CHECK-SM70-LABEL: fma_bf16_expanded_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
@@ -364,13 +323,13 @@ define bfloat @fma_bf16_expanded_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-SM70-NEXT: .reg .f32 %f<7>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_no_nans_param_2];
; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_no_nans_param_1];
; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_no_nans_param_0];
; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
@@ -402,17 +361,17 @@ define bfloat @fma_bf16_expanded_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
}
; FMA relu shouldn't be selected if the FMA operation has multiple uses
-define bfloat @fma_bf16_expanded_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_expanded_unsafe_multiple_uses_of_fma(
+define bfloat @fma_bf16_expanded_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_expanded_no_nans_multiple_uses_of_fma(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<12>;
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-NEXT: .reg .f32 %f<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_2];
; CHECK-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: mov.b16 %rs5, 0x0000;
; CHECK-NEXT: max.bf16 %rs6, %rs4, %rs5;
@@ -432,16 +391,16 @@ define bfloat @fma_bf16_expanded_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %
; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ-LABEL: fma_bf16_expanded_no_nans_multiple_uses_of_fma(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<12>;
; CHECK-FTZ-NEXT: .reg .b32 %r<7>;
; CHECK-FTZ-NEXT: .reg .f32 %f<6>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_2];
; CHECK-FTZ-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
; CHECK-FTZ-NEXT: max.bf16 %rs6, %rs4, %rs5;
@@ -461,7 +420,7 @@ define bfloat @fma_bf16_expanded_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs11;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-SM70-LABEL: fma_bf16_expanded_no_nans_multiple_uses_of_fma(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<5>;
; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
@@ -469,13 +428,13 @@ define bfloat @fma_bf16_expanded_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %
; CHECK-SM70-NEXT: .reg .f32 %f<11>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_2];
; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_1];
; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_0];
; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
@@ -528,32 +487,32 @@ define bfloat @fma_bf16_expanded_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %
ret bfloat %6
}
-define bfloat @fma_bf16_expanded_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_expanded_maxnum_unsafe(
+define bfloat @fma_bf16_expanded_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_expanded_maxnum_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_no_nans_param_2];
; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK-FTZ-LABEL: fma_bf16_expanded_maxnum_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_no_nans_param_2];
; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16_expanded_maxnum_unsafe(
+; CHECK-SM70-LABEL: fma_bf16_expanded_maxnum_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
@@ -561,13 +520,13 @@ define bfloat @fma_bf16_expanded_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c)
; CHECK-SM70-NEXT: .reg .f32 %f<7>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_maxnum_no_nans_param_2];
; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_maxnum_no_nans_param_1];
; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_maxnum_no_nans_param_0];
; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
@@ -597,41 +556,41 @@ define bfloat @fma_bf16_expanded_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c)
ret bfloat %3
}
-define <2 x half> @fma_f16x2_expanded_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
-; CHECK-LABEL: fma_f16x2_expanded_unsafe(
+define <2 x half> @fma_f16x2_expanded_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_expanded_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_param_0];
; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16x2_expanded_unsafe(
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_param_0];
; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16x2_expanded_unsafe(
+; CHECK-SM70-LABEL: fma_f16x2_expanded_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
; CHECK-SM70-NEXT: .reg .b32 %r<7>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_param_2];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_param_0];
; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
; CHECK-SM70-NEXT: mov.b32 %r5, 0;
; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
@@ -649,15 +608,15 @@ define <2 x half> @fma_f16x2_expanded_unsafe(<2 x half> %a, <2 x half> %b, <2 x
}
; FMA relu shouldn't be selected if the FMA operation has multiple uses
-define <2 x half> @fma_f16x2_expanded_unsafe_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
-; CHECK-LABEL: fma_f16x2_expanded_unsafe_multiple_uses_of_fma(
+define <2 x half> @fma_f16x2_expanded_no_nans_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_expanded_no_nans_multiple_uses_of_fma(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<10>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
; CHECK-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: mov.b32 %r5, 0;
; CHECK-NEXT: max.f16x2 %r6, %r4, %r5;
@@ -667,14 +626,14 @@ define <2 x half> @fma_f16x2_expanded_unsafe_multiple_uses_of_fma(<2 x half> %a,
; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_no_nans_multiple_uses_of_fma(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<10>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
; CHECK-FTZ-NEXT: fma.rn.ftz.f16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
; CHECK-FTZ-NEXT: max.ftz.f16x2 %r6, %r4, %r5;
@@ -684,16 +643,16 @@ define <2 x half> @fma_f16x2_expanded_unsafe_multiple_uses_of_fma(<2 x half> %a,
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r9;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-SM70-LABEL: fma_f16x2_expanded_no_nans_multiple_uses_of_fma(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
; CHECK-SM70-NEXT: .reg .b32 %r<10>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
; CHECK-SM70-NEXT: mov.b32 %r5, 0;
; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
@@ -715,56 +674,53 @@ define <2 x half> @fma_f16x2_expanded_unsafe_multiple_uses_of_fma(<2 x half> %a,
ret <2 x half> %6
}
-define <2 x half> @fma_f16x2_expanded_safe(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
-; CHECK-LABEL: fma_f16x2_expanded_safe(
+define <2 x half> @fma_f16x2_expanded_unsafe_with_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) #1 {
+; CHECK-LABEL: fma_f16x2_expanded_unsafe_with_nans(
; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<8>;
+; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_safe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_safe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_safe_param_0];
-; CHECK-NEXT: mul.rn.f16x2 %r4, %r3, %r2;
-; CHECK-NEXT: add.rn.f16x2 %r5, %r4, %r1;
-; CHECK-NEXT: mov.b32 %r6, 0;
-; CHECK-NEXT: max.f16x2 %r7, %r5, %r6;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_with_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_with_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_with_nans_param_0];
+; CHECK-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: max.f16x2 %r6, %r4, %r5;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16x2_expanded_safe(
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_unsafe_with_nans(
; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b32 %r<8>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<7>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_safe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_safe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_safe_param_0];
-; CHECK-FTZ-NEXT: mul.rn.ftz.f16x2 %r4, %r3, %r2;
-; CHECK-FTZ-NEXT: add.rn.ftz.f16x2 %r5, %r4, %r1;
-; CHECK-FTZ-NEXT: mov.b32 %r6, 0;
-; CHECK-FTZ-NEXT: max.ftz.f16x2 %r7, %r5, %r6;
-; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_with_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_with_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_with_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
+; CHECK-FTZ-NEXT: max.ftz.f16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16x2_expanded_safe(
+; CHECK-SM70-LABEL: fma_f16x2_expanded_unsafe_with_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
-; CHECK-SM70-NEXT: .reg .b32 %r<8>;
+; CHECK-SM70-NEXT: .reg .b32 %r<7>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_safe_param_2];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_safe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_safe_param_0];
-; CHECK-SM70-NEXT: mul.rn.f16x2 %r4, %r3, %r2;
-; CHECK-SM70-NEXT: add.rn.f16x2 %r5, %r4, %r1;
-; CHECK-SM70-NEXT: mov.b32 %r6, 0;
-; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r5, %r6;
-; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r5;
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_unsafe_with_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_unsafe_with_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_unsafe_with_nans_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 0;
+; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
; CHECK-SM70-NEXT: selp.b16 %rs3, %rs2, 0x0000, %p2;
; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1;
-; CHECK-SM70-NEXT: mov.b32 %r7, {%rs4, %rs3};
-; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-SM70-NEXT: mov.b32 %r6, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-SM70-NEXT: ret;
%1 = fmul <2 x half> %a, %b
%2 = fadd <2 x half> %1, %c
@@ -773,41 +729,41 @@ define <2 x half> @fma_f16x2_expanded_safe(<2 x half> %a, <2 x half> %b, <2 x ha
ret <2 x half> %4
}
-define <2 x half> @fma_f16x2_expanded_maxnum_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
-; CHECK-LABEL: fma_f16x2_expanded_maxnum_unsafe(
+define <2 x half> @fma_f16x2_expanded_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_expanded_maxnum_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_unsafe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_no_nans_param_0];
; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16x2_expanded_maxnum_unsafe(
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_maxnum_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_no_nans_param_0];
; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16x2_expanded_maxnum_unsafe(
+; CHECK-SM70-LABEL: fma_f16x2_expanded_maxnum_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
; CHECK-SM70-NEXT: .reg .b32 %r<6>;
; CHECK-SM70-NEXT: .reg .f32 %f<5>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_unsafe_param_2];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_no_nans_param_0];
; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs2;
@@ -825,189 +781,95 @@ define <2 x half> @fma_f16x2_expanded_maxnum_unsafe(<2 x half> %a, <2 x half> %b
ret <2 x half> %3
}
-define <2 x bfloat> @fma_bf16x2_expanded_safe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
-; CHECK-LABEL: fma_bf16x2_expanded_safe(
+define <2 x bfloat> @fma_bf16x2_expanded_unsafe_with_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #1 {
+; CHECK-LABEL: fma_bf16x2_expanded_unsafe_with_nans(
; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<19>;
-; CHECK-NEXT: .reg .b32 %r<23>;
-; CHECK-NEXT: .reg .f32 %f<13>;
+; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_safe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_safe_param_0];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_safe_param_1];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r3;
-; CHECK-NEXT: cvt.u32.u16 %r4, %rs1;
-; CHECK-NEXT: shl.b32 %r5, %r4, 16;
-; CHECK-NEXT: mov.b32 %f1, %r5;
-; CHECK-NEXT: mov.b32 {%rs4, %rs5}, %r2;
-; CHECK-NEXT: cvt.u32.u16 %r6, %rs4;
-; CHECK-NEXT: shl.b32 %r7, %r6, 16;
-; CHECK-NEXT: mov.b32 %f2, %r7;
-; CHECK-NEXT: mul.rn.f32 %f3, %f2, %f1;
-; CHECK-NEXT: cvt.rn.bf16.f32 %rs7, %f3;
-; CHECK-NEXT: cvt.u32.u16 %r8, %rs2;
-; CHECK-NEXT: shl.b32 %r9, %r8, 16;
-; CHECK-NEXT: mov.b32 %f4, %r9;
-; CHECK-NEXT: cvt.u32.u16 %r10, %rs5;
-; CHECK-NEXT: shl.b32 %r11, %r10, 16;
-; CHECK-NEXT: mov.b32 %f5, %r11;
-; CHECK-NEXT: mul.rn.f32 %f6, %f5, %f4;
-; CHECK-NEXT: cvt.rn.bf16.f32 %rs10, %f6;
-; CHECK-NEXT: cvt.u32.u16 %r12, %rs10;
-; CHECK-NEXT: shl.b32 %r13, %r12, 16;
-; CHECK-NEXT: mov.b32 %f7, %r13;
-; CHECK-NEXT: mov.b32 {%rs12, %rs13}, %r1;
-; CHECK-NEXT: cvt.u32.u16 %r14, %rs13;
-; CHECK-NEXT: shl.b32 %r15, %r14, 16;
-; CHECK-NEXT: mov.b32 %f8, %r15;
-; CHECK-NEXT: add.rn.f32 %f9, %f7, %f8;
-; CHECK-NEXT: cvt.rn.bf16.f32 %rs15, %f9;
-; CHECK-NEXT: cvt.u32.u16 %r16, %rs7;
-; CHECK-NEXT: shl.b32 %r17, %r16, 16;
-; CHECK-NEXT: mov.b32 %f10, %r17;
-; CHECK-NEXT: cvt.u32.u16 %r18, %rs12;
-; CHECK-NEXT: shl.b32 %r19, %r18, 16;
-; CHECK-NEXT: mov.b32 %f11, %r19;
-; CHECK-NEXT: add.rn.f32 %f12, %f10, %f11;
-; CHECK-NEXT: cvt.rn.bf16.f32 %rs18, %f12;
-; CHECK-NEXT: mov.b32 %r20, {%rs18, %rs15};
-; CHECK-NEXT: mov.b32 %r21, 0;
-; CHECK-NEXT: max.bf16x2 %r22, %r20, %r21;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r22;
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_with_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_with_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_with_nans_param_0];
+; CHECK-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: max.bf16x2 %r6, %r4, %r5;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16x2_expanded_safe(
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_unsafe_with_nans(
; CHECK-FTZ: {
-; CHECK-FTZ-NEXT: .reg .b16 %rs<19>;
-; CHECK-FTZ-NEXT: .reg .b32 %r<23>;
-; CHECK-FTZ-NEXT: .reg .f32 %f<13>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<7>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_safe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_safe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_safe_param_1];
-; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r3;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r4, %rs1;
-; CHECK-FTZ-NEXT: shl.b32 %r5, %r4, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f1, %r5;
-; CHECK-FTZ-NEXT: mov.b32 {%rs4, %rs5}, %r2;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r6, %rs4;
-; CHECK-FTZ-NEXT: shl.b32 %r7, %r6, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f2, %r7;
-; CHECK-FTZ-NEXT: mul.rn.ftz.f32 %f3, %f2, %f1;
-; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs7, %f3;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r8, %rs2;
-; CHECK-FTZ-NEXT: shl.b32 %r9, %r8, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f4, %r9;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r10, %rs5;
-; CHECK-FTZ-NEXT: shl.b32 %r11, %r10, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f5, %r11;
-; CHECK-FTZ-NEXT: mul.rn.ftz.f32 %f6, %f5, %f4;
-; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs10, %f6;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r12, %rs10;
-; CHECK-FTZ-NEXT: shl.b32 %r13, %r12, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f7, %r13;
-; CHECK-FTZ-NEXT: mov.b32 {%rs12, %rs13}, %r1;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r14, %rs13;
-; CHECK-FTZ-NEXT: shl.b32 %r15, %r14, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f8, %r15;
-; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f9, %f7, %f8;
-; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs15, %f9;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r16, %rs7;
-; CHECK-FTZ-NEXT: shl.b32 %r17, %r16, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f10, %r17;
-; CHECK-FTZ-NEXT: cvt.u32.u16 %r18, %rs12;
-; CHECK-FTZ-NEXT: shl.b32 %r19, %r18, 16;
-; CHECK-FTZ-NEXT: mov.b32 %f11, %r19;
-; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f12, %f10, %f11;
-; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs18, %f12;
-; CHECK-FTZ-NEXT: mov.b32 %r20, {%rs18, %rs15};
-; CHECK-FTZ-NEXT: mov.b32 %r21, 0;
-; CHECK-FTZ-NEXT: max.bf16x2 %r22, %r20, %r21;
-; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r22;
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_with_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_with_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_with_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
+; CHECK-FTZ-NEXT: max.bf16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16x2_expanded_safe(
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_unsafe_with_nans(
; CHECK-SM70: {
-; CHECK-SM70-NEXT: .reg .pred %p<7>;
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
; CHECK-SM70-NEXT: .reg .b16 %rs<19>;
-; CHECK-SM70-NEXT: .reg .b32 %r<45>;
-; CHECK-SM70-NEXT: .reg .f32 %f<15>;
+; CHECK-SM70-NEXT: .reg .b32 %r<31>;
+; CHECK-SM70-NEXT: .reg .f32 %f<11>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_safe_param_2];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_safe_param_0];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_safe_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_with_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_with_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_with_nans_param_2];
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
-; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
-; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs5;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
-; CHECK-SM70-NEXT: mul.rn.f32 %f3, %f2, %f1;
-; CHECK-SM70-NEXT: mov.b32 %r8, %f3;
-; CHECK-SM70-NEXT: bfe.u32 %r9, %r8, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r10, %r9, %r8;
-; CHECK-SM70-NEXT: add.s32 %r11, %r10, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f3, %f3;
-; CHECK-SM70-NEXT: or.b32 %r12, %r8, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r13, %r12, %r11, %p1;
-; CHECK-SM70-NEXT: cvt.u32.u16 %r14, %rs1;
-; CHECK-SM70-NEXT: shl.b32 %r15, %r14, 16;
-; CHECK-SM70-NEXT: mov.b32 %f4, %r15;
-; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs4;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r15; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
-; CHECK-SM70-NEXT: mul.rn.f32 %f6, %f5, %f4;
-; CHECK-SM70-NEXT: mov.b32 %r18, %f6;
-; CHECK-SM70-NEXT: bfe.u32 %r19, %r18, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r20, %r19, %r18;
-; CHECK-SM70-NEXT: add.s32 %r21, %r20, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
-; CHECK-SM70-NEXT: or.b32 %r22, %r18, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r23, %r22, %r21, %p2;
-; CHECK-SM70-NEXT: and.b32 %r24, %r23, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f7, %r24;
-; CHECK-SM70-NEXT: mov.b32 {%rs9, %rs10}, %r1;
-; CHECK-SM70-NEXT: cvt.u32.u16 %r25, %rs9;
-; CHECK-SM70-NEXT: shl.b32 %r26, %r25, 16;
-; CHECK-SM70-NEXT: mov.b32 %f8, %r26;
-; CHECK-SM70-NEXT: add.rn.f32 %f9, %f7, %f8;
-; CHECK-SM70-NEXT: mov.b32 %r27, %f9;
-; CHECK-SM70-NEXT: bfe.u32 %r28, %r27, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r29, %r28, %r27;
-; CHECK-SM70-NEXT: add.s32 %r30, %r29, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f9, %f9;
-; CHECK-SM70-NEXT: or.b32 %r31, %r27, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r32, %r31, %r30, %p3;
-; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs12}, %r32; }
-; CHECK-SM70-NEXT: and.b32 %r33, %r13, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f10, %r33;
-; CHECK-SM70-NEXT: cvt.u32.u16 %r34, %rs10;
-; CHECK-SM70-NEXT: shl.b32 %r35, %r34, 16;
-; CHECK-SM70-NEXT: mov.b32 %f11, %r35;
-; CHECK-SM70-NEXT: add.rn.f32 %f12, %f10, %f11;
-; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
-; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
-; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
-; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
-; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f12, %f12;
-; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
-; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p4;
-; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r41; }
-; CHECK-SM70-NEXT: and.b32 %r42, %r32, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f13, %r42;
-; CHECK-SM70-NEXT: setp.gt.f32 %p5, %f13, 0f00000000;
-; CHECK-SM70-NEXT: and.b32 %r43, %r41, -65536;
-; CHECK-SM70-NEXT: mov.b32 %f14, %r43;
-; CHECK-SM70-NEXT: setp.gt.f32 %p6, %f14, 0f00000000;
-; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p6;
-; CHECK-SM70-NEXT: selp.b16 %rs18, %rs12, 0x0000, %p5;
-; CHECK-SM70-NEXT: mov.b32 %r44, {%rs18, %rs17};
-; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r44;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r27; }
+; CHECK-SM70-NEXT: and.b32 %r28, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: setp.gt.f32 %p3, %f9, 0f00000000;
+; CHECK-SM70-NEXT: and.b32 %r29, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f10, %r29;
+; CHECK-SM70-NEXT: setp.gt.f32 %p4, %f10, 0f00000000;
+; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p4;
+; CHECK-SM70-NEXT: selp.b16 %rs18, %rs10, 0x0000, %p3;
+; CHECK-SM70-NEXT: mov.b32 %r30, {%rs18, %rs17};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r30;
; CHECK-SM70-NEXT: ret;
%1 = fmul <2 x bfloat> %a, %b
%2 = fadd <2 x bfloat> %1, %c
@@ -1016,32 +878,32 @@ define <2 x bfloat> @fma_bf16x2_expanded_safe(<2 x bfloat> %a, <2 x bfloat> %b,
ret <2 x bfloat> %4
}
-define <2 x bfloat> @fma_bf16x2_expanded_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
-; CHECK-LABEL: fma_bf16x2_expanded_unsafe(
+define <2 x bfloat> @fma_bf16x2_expanded_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_expanded_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_param_0];
; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16x2_expanded_unsafe(
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_param_0];
; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16x2_expanded_unsafe(
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<5>;
; CHECK-SM70-NEXT: .reg .b16 %rs<19>;
@@ -1049,9 +911,9 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe(<2 x bfloat> %a, <2 x bfloat> %b
; CHECK-SM70-NEXT: .reg .f32 %f<11>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_param_2];
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
@@ -1110,17 +972,17 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe(<2 x bfloat> %a, <2 x bfloat> %b
}
; FMA relu shouldn't be selected if the FMA operation has multiple uses
-define <2 x bfloat> @fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
-; CHECK-LABEL: fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(
+define <2 x bfloat> @fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<15>;
; CHECK-NEXT: .reg .b32 %r<20>;
; CHECK-NEXT: .reg .f32 %f<11>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
; CHECK-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: mov.b32 %r5, 0;
; CHECK-NEXT: max.bf16x2 %r6, %r4, %r5;
@@ -1156,16 +1018,16 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(<2 x bfloat
; CHECK-NEXT: st.param.b32 [func_retval0], %r19;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<15>;
; CHECK-FTZ-NEXT: .reg .b32 %r<20>;
; CHECK-FTZ-NEXT: .reg .f32 %f<11>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
; CHECK-FTZ-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
; CHECK-FTZ-NEXT: max.bf16x2 %r6, %r4, %r5;
@@ -1201,7 +1063,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(<2 x bfloat
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r19;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<9>;
; CHECK-SM70-NEXT: .reg .b16 %rs<25>;
@@ -1209,9 +1071,9 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(<2 x bfloat
; CHECK-SM70-NEXT: .reg .f32 %f<19>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs2;
; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
@@ -1315,32 +1177,32 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe_multiple_uses_of_fma(<2 x bfloat
ret <2 x bfloat> %6
}
-define <2 x bfloat> @fma_bf16x2_expanded_maxnum_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
-; CHECK-LABEL: fma_bf16x2_expanded_maxnum_unsafe(
+define <2 x bfloat> @fma_bf16x2_expanded_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_expanded_maxnum_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_unsafe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_no_nans_param_0];
; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16x2_expanded_maxnum_unsafe(
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_maxnum_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_no_nans_param_0];
; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16x2_expanded_maxnum_unsafe(
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_maxnum_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<5>;
; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
@@ -1348,9 +1210,9 @@ define <2 x bfloat> @fma_bf16x2_expanded_maxnum_unsafe(<2 x bfloat> %a, <2 x bfl
; CHECK-SM70-NEXT: .reg .f32 %f<13>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_no_nans_param_2];
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
@@ -1419,4 +1281,5 @@ define <2 x bfloat> @fma_bf16x2_expanded_maxnum_unsafe(<2 x bfloat> %a, <2 x bfl
ret <2 x bfloat> %3
}
-attributes #0 = { "unsafe-fp-math"="true" }
+attributes #0 = { "no-nans-fp-math"="true" "unsafe-fp-math"="true" }
+attributes #1 = { "unsafe-fp-math"="true" }
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
index 6fdaf9f911e45c..59a2bf94de0450 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
@@ -9,40 +9,40 @@
; SM < 80 or (which needs PTX version >= 70) should not emit fma{.ftz}.relu
; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 | FileCheck %s --check-prefixes=CHECK-SM70
-define half @fma_f16_unsafe(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_unsafe(
+define half @fma_f16_no_nans(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_param_2];
; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16_unsafe(
+; CHECK-FTZ-LABEL: fma_f16_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_param_2];
; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16_unsafe(
+; CHECK-SM70-LABEL: fma_f16_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
; CHECK-SM70-NEXT: .reg .f32 %f<3>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_param_2];
; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
@@ -56,15 +56,15 @@ define half @fma_f16_unsafe(half %a, half %b, half %c) #0 {
}
; FMA relu shouldn't be selected if the FMA operation has multiple uses
-define half @fma_f16_unsafe_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_unsafe_multiple_uses_of_fma(
+define half @fma_f16_no_nans_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_no_nans_multiple_uses_of_fma(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_multiple_uses_of_fma_param_2];
; CHECK-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: mov.b16 %rs5, 0x4700;
; CHECK-NEXT: add.f16 %rs6, %rs4, %rs5;
@@ -72,14 +72,14 @@ define half @fma_f16_unsafe_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
; CHECK-NEXT: st.param.b16 [func_retval0], %rs7;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ-LABEL: fma_f16_no_nans_multiple_uses_of_fma(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<8>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_multiple_uses_of_fma_param_2];
; CHECK-FTZ-NEXT: fma.rn.ftz.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x4700;
; CHECK-FTZ-NEXT: add.ftz.f16 %rs6, %rs4, %rs5;
@@ -87,14 +87,14 @@ define half @fma_f16_unsafe_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs7;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16_unsafe_multiple_uses_of_fma(
+; CHECK-SM70-LABEL: fma_f16_no_nans_multiple_uses_of_fma(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b16 %rs<8>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_multiple_uses_of_fma_param_2];
; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-SM70-NEXT: mov.b16 %rs5, 0x4700;
; CHECK-SM70-NEXT: add.f16 %rs6, %rs4, %rs5;
@@ -109,40 +109,40 @@ define half @fma_f16_unsafe_multiple_uses_of_fma(half %a, half %b, half %c) #0 {
ret half %5
}
-define half @fma_f16_maxnum_unsafe(half %a, half %b, half %c) #0 {
-; CHECK-LABEL: fma_f16_maxnum_unsafe(
+define half @fma_f16_maxnum_no_nans(half %a, half %b, half %c) #0 {
+; CHECK-LABEL: fma_f16_maxnum_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_no_nans_param_2];
; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16_maxnum_unsafe(
+; CHECK-FTZ-LABEL: fma_f16_maxnum_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_no_nans_param_2];
; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16_maxnum_unsafe(
+; CHECK-SM70-LABEL: fma_f16_maxnum_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
; CHECK-SM70-NEXT: .reg .f32 %f<3>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_no_nans_param_2];
; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
@@ -154,32 +154,32 @@ define half @fma_f16_maxnum_unsafe(half %a, half %b, half %c) #0 {
ret half %2
}
-define bfloat @fma_bf16_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_unsafe(
+define bfloat @fma_bf16_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_no_nans_param_2];
; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16_unsafe(
+; CHECK-FTZ-LABEL: fma_bf16_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_no_nans_param_2];
; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16_unsafe(
+; CHECK-SM70-LABEL: fma_bf16_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
@@ -187,13 +187,13 @@ define bfloat @fma_bf16_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-SM70-NEXT: .reg .f32 %f<7>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_no_nans_param_2];
; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_no_nans_param_1];
; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_no_nans_param_0];
; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
@@ -224,17 +224,17 @@ define bfloat @fma_bf16_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
}
; FMA_relu shouldn't be selected if the FMA operation has multiple uses
-define bfloat @fma_bf16_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_unsafe_multiple_uses_of_fma(
+define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_no_nans_multiple_uses_of_fma(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<9>;
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-NEXT: .reg .f32 %f<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_no_nans_multiple_uses_of_fma_param_2];
; CHECK-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: cvt.u32.u16 %r1, %rs4;
; CHECK-NEXT: shl.b32 %r2, %r1, 16;
@@ -249,16 +249,16 @@ define bfloat @fma_bf16_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat
; CHECK-NEXT: st.param.b16 [func_retval0], %rs8;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ-LABEL: fma_bf16_no_nans_multiple_uses_of_fma(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<9>;
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-NEXT: .reg .f32 %f<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_no_nans_multiple_uses_of_fma_param_2];
; CHECK-FTZ-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: cvt.u32.u16 %r1, %rs4;
; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
@@ -273,7 +273,7 @@ define bfloat @fma_bf16_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs8;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16_unsafe_multiple_uses_of_fma(
+; CHECK-SM70-LABEL: fma_bf16_no_nans_multiple_uses_of_fma(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<4>;
; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
@@ -281,13 +281,13 @@ define bfloat @fma_bf16_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat
; CHECK-SM70-NEXT: .reg .f32 %f<9>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_no_nans_multiple_uses_of_fma_param_2];
; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_unsafe_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_no_nans_multiple_uses_of_fma_param_1];
; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_no_nans_multiple_uses_of_fma_param_0];
; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
@@ -329,32 +329,32 @@ define bfloat @fma_bf16_unsafe_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat
ret bfloat %5
}
-define bfloat @fma_bf16_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
-; CHECK-LABEL: fma_bf16_maxnum_unsafe(
+define bfloat @fma_bf16_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 {
+; CHECK-LABEL: fma_bf16_maxnum_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_no_nans_param_2];
; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK-FTZ-LABEL: fma_bf16_maxnum_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_unsafe_param_0];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_no_nans_param_2];
; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16_maxnum_unsafe(
+; CHECK-SM70-LABEL: fma_bf16_maxnum_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
@@ -362,13 +362,13 @@ define bfloat @fma_bf16_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-SM70-NEXT: .reg .f32 %f<7>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_maxnum_no_nans_param_2];
; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
-; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_maxnum_unsafe_param_1];
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_maxnum_no_nans_param_1];
; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
-; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_maxnum_no_nans_param_0];
; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
@@ -397,41 +397,41 @@ define bfloat @fma_bf16_maxnum_unsafe(bfloat %a, bfloat %b, bfloat %c) #0 {
ret bfloat %2
}
-define <2 x half> @fma_f16x2_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
-; CHECK-LABEL: fma_f16x2_unsafe(
+define <2 x half> @fma_f16x2_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_param_0];
; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16x2_unsafe(
+; CHECK-FTZ-LABEL: fma_f16x2_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_param_0];
; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16x2_unsafe(
+; CHECK-SM70-LABEL: fma_f16x2_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<3>;
; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
; CHECK-SM70-NEXT: .reg .b32 %r<7>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_param_2];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_param_0];
; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
; CHECK-SM70-NEXT: mov.b32 %r5, 0;
; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
@@ -448,15 +448,15 @@ define <2 x half> @fma_f16x2_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c)
}
; FMA relu shouldn't be selected if the FMA operation has multiple uses
-define <2 x half> @fma_f16x2_unsafe_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
-; CHECK-LABEL: fma_f16x2_unsafe_multiple_uses_of_fma(
+define <2 x half> @fma_f16x2_no_nans_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_no_nans_multiple_uses_of_fma(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_multiple_uses_of_fma_param_0];
; CHECK-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: mov.b32 %r5, 1191200512;
; CHECK-NEXT: add.f16x2 %r6, %r4, %r5;
@@ -464,14 +464,14 @@ define <2 x half> @fma_f16x2_unsafe_multiple_uses_of_fma(<2 x half> %a, <2 x hal
; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16x2_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ-LABEL: fma_f16x2_no_nans_multiple_uses_of_fma(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<8>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_multiple_uses_of_fma_param_0];
; CHECK-FTZ-NEXT: fma.rn.ftz.f16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: mov.b32 %r5, 1191200512;
; CHECK-FTZ-NEXT: add.ftz.f16x2 %r6, %r4, %r5;
@@ -479,14 +479,14 @@ define <2 x half> @fma_f16x2_unsafe_multiple_uses_of_fma(<2 x half> %a, <2 x hal
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16x2_unsafe_multiple_uses_of_fma(
+; CHECK-SM70-LABEL: fma_f16x2_no_nans_multiple_uses_of_fma(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b32 %r<8>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_multiple_uses_of_fma_param_0];
; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
; CHECK-SM70-NEXT: mov.b32 %r5, 1191200512;
; CHECK-SM70-NEXT: add.f16x2 %r6, %r4, %r5;
@@ -501,41 +501,41 @@ define <2 x half> @fma_f16x2_unsafe_multiple_uses_of_fma(<2 x half> %a, <2 x hal
ret <2 x half> %5
}
-define <2 x half> @fma_f16x2_maxnum_unsafe(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
-; CHECK-LABEL: fma_f16x2_maxnum_unsafe(
+define <2 x half> @fma_f16x2_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-LABEL: fma_f16x2_maxnum_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_unsafe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_no_nans_param_0];
; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_f16x2_maxnum_unsafe(
+; CHECK-FTZ-LABEL: fma_f16x2_maxnum_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_no_nans_param_0];
; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_f16x2_maxnum_unsafe(
+; CHECK-SM70-LABEL: fma_f16x2_maxnum_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
; CHECK-SM70-NEXT: .reg .b32 %r<6>;
; CHECK-SM70-NEXT: .reg .f32 %f<5>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_unsafe_param_2];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_unsafe_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_no_nans_param_0];
; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs2;
@@ -552,32 +552,32 @@ define <2 x half> @fma_f16x2_maxnum_unsafe(<2 x half> %a, <2 x half> %b, <2 x ha
ret <2 x half> %2
}
-define <2 x bfloat> @fma_bf16x2_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
-; CHECK-LABEL: fma_bf16x2_unsafe(
+define <2 x bfloat> @fma_bf16x2_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_param_0];
; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16x2_unsafe(
+; CHECK-FTZ-LABEL: fma_bf16x2_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_param_0];
; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16x2_unsafe(
+; CHECK-SM70-LABEL: fma_bf16x2_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<5>;
; CHECK-SM70-NEXT: .reg .b16 %rs<19>;
@@ -585,9 +585,9 @@ define <2 x bfloat> @fma_bf16x2_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bf
; CHECK-SM70-NEXT: .reg .f32 %f<11>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_param_2];
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
@@ -645,17 +645,17 @@ define <2 x bfloat> @fma_bf16x2_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bf
}
; FMA_relu shouldn't be selected if the FMA operation has multiple uses
-define <2 x bfloat> @fma_bf16x2_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
-; CHECK-LABEL: fma_bf16x2_unsafe_multiple_uses_of_fma(
+define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_no_nans_multiple_uses_of_fma(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<11>;
; CHECK-NEXT: .reg .b32 %r<14>;
; CHECK-NEXT: .reg .f32 %f<9>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_0];
; CHECK-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r4;
; CHECK-NEXT: cvt.u32.u16 %r5, %rs1;
@@ -682,16 +682,16 @@ define <2 x bfloat> @fma_bf16x2_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2
; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16x2_unsafe_multiple_uses_of_fma(
+; CHECK-FTZ-LABEL: fma_bf16x2_no_nans_multiple_uses_of_fma(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b16 %rs<11>;
; CHECK-FTZ-NEXT: .reg .b32 %r<14>;
; CHECK-FTZ-NEXT: .reg .f32 %f<9>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_0];
; CHECK-FTZ-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r4;
; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs1;
@@ -718,7 +718,7 @@ define <2 x bfloat> @fma_bf16x2_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16x2_unsafe_multiple_uses_of_fma(
+; CHECK-SM70-LABEL: fma_bf16x2_no_nans_multiple_uses_of_fma(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<7>;
; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
@@ -726,9 +726,9 @@ define <2 x bfloat> @fma_bf16x2_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2
; CHECK-SM70-NEXT: .reg .f32 %f<17>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_0];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_unsafe_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_2];
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs2;
; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
@@ -819,32 +819,32 @@ define <2 x bfloat> @fma_bf16x2_unsafe_multiple_uses_of_fma(<2 x bfloat> %a, <2
ret <2 x bfloat> %5
}
-define <2 x bfloat> @fma_bf16x2_maxnum_unsafe(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
-; CHECK-LABEL: fma_bf16x2_maxnum_unsafe(
+define <2 x bfloat> @fma_bf16x2_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: fma_bf16x2_maxnum_no_nans(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_unsafe_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_unsafe_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_unsafe_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_no_nans_param_0];
; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
;
-; CHECK-FTZ-LABEL: fma_bf16x2_maxnum_unsafe(
+; CHECK-FTZ-LABEL: fma_bf16x2_maxnum_no_nans(
; CHECK-FTZ: {
; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-FTZ-EMPTY:
; CHECK-FTZ-NEXT: // %bb.0:
-; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_unsafe_param_2];
-; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_unsafe_param_1];
-; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_unsafe_param_0];
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_no_nans_param_0];
; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-FTZ-NEXT: ret;
;
-; CHECK-SM70-LABEL: fma_bf16x2_maxnum_unsafe(
+; CHECK-SM70-LABEL: fma_bf16x2_maxnum_no_nans(
; CHECK-SM70: {
; CHECK-SM70-NEXT: .reg .pred %p<5>;
; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
@@ -852,9 +852,9 @@ define <2 x bfloat> @fma_bf16x2_maxnum_unsafe(<2 x bfloat> %a, <2 x bfloat> %b,
; CHECK-SM70-NEXT: .reg .f32 %f<13>;
; CHECK-SM70-EMPTY:
; CHECK-SM70-NEXT: // %bb.0:
-; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_unsafe_param_0];
-; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_unsafe_param_1];
-; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_unsafe_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_no_nans_param_2];
; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
@@ -922,4 +922,5 @@ define <2 x bfloat> @fma_bf16x2_maxnum_unsafe(<2 x bfloat> %a, <2 x bfloat> %b,
ret <2 x bfloat> %2
}
-attributes #0 = { "unsafe-fp-math"="true" }
+attributes #0 = { "no-nans-fp-math"="true" "unsafe-fp-math"="true" }
+attributes #1 = { "unsafe-fp-math"="true" }
>From 3a99a4f760fac4892790b77f1d7c4cf78690e99a Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Fri, 8 Nov 2024 13:15:50 +0000
Subject: [PATCH 08/14] Make fpimm match negative zeros as well
Extend the pattern to allow negative zeros for scalar types.
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 5bd76949960f0c..48fece07c18627 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3905,8 +3905,8 @@ def atomic_thread_fence_acq_rel_cta :
NVPTXInst<(outs), (ins), "fence.acq_rel.cta;", []>,
Requires<[hasPTX<60>, hasSM<70>]>;
-def fpimm_positive_zero : FPImmLeaf<fAny, [{
- return Imm.isExactlyValue(+0.0);
+def fpimm_pos_neg_zero : FPImmLeaf<fAny, [{
+ return Imm.isExactlyValue(+0.0) | Imm.isExactlyValue(-0.0);
}]>;
def fpimm_positive_zero_v2f16 : PatFrag<(ops), (v2f16 (bitconvert (i32 0)))>;
@@ -3945,17 +3945,17 @@ def FMARELU_F16X2_FTZ :
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
// FTZ variants are only supported by fp16, not bf16
-def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_pos_neg_zero)),
(FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, noNaNsFPMath]>;
def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
(FMARELU_F16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
Requires<[doF32FTZ, noNaNsFPMath]>;
// No FTZ
-def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_pos_neg_zero)),
(FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[noNaNsFPMath]>;
-def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_positive_zero)),
+def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_pos_neg_zero)),
(FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[noNaNsFPMath]>;
def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
>From 81e79c7beb1244e90721ddab54310c58b4f91d1a Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Mon, 11 Nov 2024 09:47:57 +0000
Subject: [PATCH 09/14] Rename pos_neg_zero to any_zero
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 48fece07c18627..92c670863f0b1e 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3905,7 +3905,7 @@ def atomic_thread_fence_acq_rel_cta :
NVPTXInst<(outs), (ins), "fence.acq_rel.cta;", []>,
Requires<[hasPTX<60>, hasSM<70>]>;
-def fpimm_pos_neg_zero : FPImmLeaf<fAny, [{
+def fpimm_any_zero : FPImmLeaf<fAny, [{
return Imm.isExactlyValue(+0.0) | Imm.isExactlyValue(-0.0);
}]>;
@@ -3945,17 +3945,17 @@ def FMARELU_F16X2_FTZ :
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
// FTZ variants are only supported by fp16, not bf16
-def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_pos_neg_zero)),
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
(FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, noNaNsFPMath]>;
def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
(FMARELU_F16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
Requires<[doF32FTZ, noNaNsFPMath]>;
// No FTZ
-def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_pos_neg_zero)),
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
(FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[noNaNsFPMath]>;
-def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_pos_neg_zero)),
+def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
(FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[noNaNsFPMath]>;
def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
>From 964f52278588c1916e05bddccb17a4a1078faebb Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Mon, 11 Nov 2024 17:25:37 +0000
Subject: [PATCH 10/14] Allow instruction flags to emit fma_relu
If nnan is used in instruction flags then FMA relu can also be emitted.
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 23 +
.../NVPTX/fma-relu-instruction-flag.ll | 1928 +++++++++++++++++
2 files changed, 1951 insertions(+)
create mode 100644 llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 92c670863f0b1e..e5b0d616ad27eb 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3917,6 +3917,11 @@ def NVPTX_fma_oneuse : PatFrag<(ops node:$a, node:$b, node:$c),
(fma node:$a, node:$b, node:$c), [{
return N->hasOneUse();
}]>;
+// We can use the instruction flag nnan instead of relying on a function attribute
+def NVPTX_fma_oneuse_and_nnan : PatFrag<(ops node:$a, node:$b, node:$c),
+ (fma node:$a, node:$b, node:$c), [{
+ return N->hasOneUse() && N->getFlags().hasNoNaNs();
+}]>;
def FMARELU_F16 :
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
@@ -3944,7 +3949,25 @@ def FMARELU_F16X2_FTZ :
"fma.rn.ftz.relu.f16x2 \t$dst, $a, $b, $c;", []>,
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
+// Don't use function attributes, use instruction flag instead
// FTZ variants are only supported by fp16, not bf16
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
+ (FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
+ Requires<[doF32FTZ]>;
+def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
+ (FMARELU_F16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
+ Requires<[doF32FTZ]>;
+// No FTZ
+def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
+ (FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>;
+def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
+ (FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>;
+def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
+ (FMARELU_F16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>;
+def : Pat<(v2bf16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2bf16)),
+ (FMARELU_BF16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>;
+
+// Use function attributes for noNaNsFPMath, instead of instruction flag
def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
(FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ, noNaNsFPMath]>;
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll b/llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
new file mode 100644
index 00000000000000..f6d53b36c7ae0f
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
@@ -0,0 +1,1928 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; Using FTZ should emit fma.ftz.relu for f16, not for bf16
+; RUN: llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK-FTZ
+; RUN: %if ptxas %{ llc < %s -denormal-fp-math-f32=preserve-sign -march=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; SM < 80 or (which needs PTX version >= 70) should not emit fma{.ftz}.relu
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 | FileCheck %s --check-prefixes=CHECK-SM70
+
+define half @fma_f16_expanded_no_nans(half %a, half %b, half %c) {
+; CHECK-LABEL: fma_f16_expanded_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast half %a, %b
+ %2 = fadd fast half %1, %c
+ %3 = fcmp ogt half %2, 0.0
+ %4 = select i1 %3, half %2, half 0.0
+ ret half %4
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define half @fma_f16_expanded_no_nans_multiple_uses_of_fma(half %a, half %b, half %c) {
+; CHECK-LABEL: fma_f16_expanded_no_nans_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<10>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-NEXT: max.f16 %rs6, %rs4, %rs5;
+; CHECK-NEXT: mov.b16 %rs7, 0x4700;
+; CHECK-NEXT: add.rn.f16 %rs8, %rs4, %rs7;
+; CHECK-NEXT: add.rn.f16 %rs9, %rs6, %rs8;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs9;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_no_nans_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<10>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-FTZ-NEXT: max.ftz.f16 %rs6, %rs4, %rs5;
+; CHECK-FTZ-NEXT: mov.b16 %rs7, 0x4700;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16 %rs8, %rs4, %rs7;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16 %rs9, %rs6, %rs8;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs9;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_no_nans_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<9>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: mov.b16 %rs6, 0x4700;
+; CHECK-SM70-NEXT: add.rn.f16 %rs7, %rs4, %rs6;
+; CHECK-SM70-NEXT: add.rn.f16 %rs8, %rs5, %rs7;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs8;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast half %a, %b
+ %2 = fadd fast half %1, %c
+ %3 = fcmp ogt half %2, 0.0
+ %4 = select i1 %3, half %2, half 0.0
+ %5 = fadd half %2, 7.0
+ %6 = fadd half %4, %5
+ ret half %6
+}
+
+define half @fma_f16_expanded_maxnum_no_nans(half %a, half %b, half %c) {
+; CHECK-LABEL: fma_f16_expanded_maxnum_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_no_nans_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_expanded_maxnum_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_expanded_maxnum_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_expanded_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_expanded_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_expanded_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast half %a, %b
+ %2 = fadd fast half %1, %c
+ %3 = call half @llvm.maxnum.f16(half %2, half 0.0)
+ ret half %3
+}
+
+define bfloat @fma_bf16_expanded_no_nans(bfloat %a, bfloat %b, bfloat %c) {
+; CHECK-LABEL: fma_bf16_expanded_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_no_nans_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_no_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_no_nans_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_no_nans_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_no_nans_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast bfloat %a, %b
+ %2 = fadd fast bfloat %1, %c
+ %3 = fcmp ogt bfloat %2, 0.0
+ %4 = select i1 %3, bfloat %2, bfloat 0.0
+ ret bfloat %4
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define bfloat @fma_bf16_expanded_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) {
+; CHECK-LABEL: fma_bf16_expanded_no_nans_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<12>;
+; CHECK-NEXT: .reg .b32 %r<7>;
+; CHECK-NEXT: .reg .f32 %f<6>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-NEXT: max.bf16 %rs6, %rs4, %rs5;
+; CHECK-NEXT: cvt.u32.u16 %r1, %rs4;
+; CHECK-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-NEXT: mov.b32 %f1, %r2;
+; CHECK-NEXT: add.rn.f32 %f2, %f1, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs8, %f2;
+; CHECK-NEXT: cvt.u32.u16 %r3, %rs6;
+; CHECK-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-NEXT: mov.b32 %f3, %r4;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs8;
+; CHECK-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-NEXT: mov.b32 %f4, %r6;
+; CHECK-NEXT: add.rn.f32 %f5, %f3, %f4;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs11, %f5;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_no_nans_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<12>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<7>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<6>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x0000;
+; CHECK-FTZ-NEXT: max.bf16 %rs6, %rs4, %rs5;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r1, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f2, %f1, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs8, %f2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r3, %rs6;
+; CHECK-FTZ-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f3, %r4;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs8;
+; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f4, %r6;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f5, %f3, %f4;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs11, %f5;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_no_nans_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<34>;
+; CHECK-SM70-NEXT: .reg .f32 %f<11>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: add.rn.f32 %f7, %f5, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r20, %f7;
+; CHECK-SM70-NEXT: bfe.u32 %r21, %r20, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r22, %r21, %r20;
+; CHECK-SM70-NEXT: add.s32 %r23, %r22, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f7, %f7;
+; CHECK-SM70-NEXT: or.b32 %r24, %r20, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r25, %r24, %r23, %p3;
+; CHECK-SM70-NEXT: and.b32 %r26, %r25, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f8, %r26;
+; CHECK-SM70-NEXT: and.b32 %r27, %r19, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r27;
+; CHECK-SM70-NEXT: add.rn.f32 %f10, %f9, %f8;
+; CHECK-SM70-NEXT: mov.b32 %r28, %f10;
+; CHECK-SM70-NEXT: bfe.u32 %r29, %r28, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r30, %r29, %r28;
+; CHECK-SM70-NEXT: add.s32 %r31, %r30, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f10, %f10;
+; CHECK-SM70-NEXT: or.b32 %r32, %r28, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r33, %r32, %r31, %p4;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r33; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast bfloat %a, %b
+ %2 = fadd fast bfloat %1, %c
+ %3 = fcmp ogt bfloat %2, 0.0
+ %4 = select i1 %3, bfloat %2, bfloat 0.0
+ %5 = fadd bfloat %2, 7.0
+ %6 = fadd bfloat %4, %5
+ ret bfloat %6
+}
+
+define bfloat @fma_bf16_expanded_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) {
+;
+;
+; CHECK-LABEL: fma_bf16_expanded_maxnum_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_no_nans_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_expanded_maxnum_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_expanded_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_expanded_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_expanded_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_expanded_maxnum_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_expanded_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_expanded_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_expanded_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast bfloat %a, %b
+ %2 = fadd fast bfloat %1, %c
+ %3 = call bfloat @llvm.maxnum.bf16(bfloat %2, bfloat 0.0)
+ ret bfloat %3
+}
+
+define <2 x half> @fma_f16x2_expanded_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
+;
+;
+; CHECK-LABEL: fma_f16x2_expanded_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_param_0];
+; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_expanded_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 0;
+; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: selp.b16 %rs3, %rs2, 0x0000, %p2;
+; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1;
+; CHECK-SM70-NEXT: mov.b32 %r6, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast <2 x half> %a, %b
+ %2 = fadd fast <2 x half> %1, %c
+ %3 = fcmp ogt <2 x half> %2, <half 0.0, half 0.0>
+ %4 = select <2 x i1> %3, <2 x half> %2, <2 x half> <half 0.0, half 0.0>
+ ret <2 x half> %4
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define <2 x half> @fma_f16x2_expanded_no_nans_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
+;
+;
+; CHECK-LABEL: fma_f16x2_expanded_no_nans_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<10>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: max.f16x2 %r6, %r4, %r5;
+; CHECK-NEXT: mov.b32 %r7, 1191200512;
+; CHECK-NEXT: add.rn.f16x2 %r8, %r4, %r7;
+; CHECK-NEXT: add.rn.f16x2 %r9, %r6, %r8;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_no_nans_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<10>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
+; CHECK-FTZ-NEXT: max.ftz.f16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: mov.b32 %r7, 1191200512;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16x2 %r8, %r4, %r7;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16x2 %r9, %r6, %r8;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_expanded_no_nans_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<10>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 0;
+; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: selp.b16 %rs3, %rs2, 0x0000, %p2;
+; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1;
+; CHECK-SM70-NEXT: mov.b32 %r6, {%rs4, %rs3};
+; CHECK-SM70-NEXT: mov.b32 %r7, 1191200512;
+; CHECK-SM70-NEXT: add.rn.f16x2 %r8, %r4, %r7;
+; CHECK-SM70-NEXT: add.rn.f16x2 %r9, %r6, %r8;
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast <2 x half> %a, %b
+ %2 = fadd fast <2 x half> %1, %c
+ %3 = fcmp ogt <2 x half> %2, <half 0.0, half 0.0>
+ %4 = select <2 x i1> %3, <2 x half> %2, <2 x half> <half 0.0, half 0.0>
+ %5 = fadd <2 x half> %2, <half 7.0, half 7.0>
+ %6 = fadd <2 x half> %4, %5
+ ret <2 x half> %6
+}
+
+define <2 x half> @fma_f16x2_expanded_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
+; CHECK-LABEL: fma_f16x2_expanded_maxnum_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_no_nans_param_0];
+; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_expanded_maxnum_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_expanded_maxnum_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<5>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_expanded_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-SM70-NEXT: max.f32 %f4, %f3, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-SM70-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast <2 x half> %a, %b
+ %2 = fadd fast <2 x half> %1, %c
+ %3 = call <2 x half> @llvm.maxnum.f16x2(<2 x half> %2, <2 x half> <half 0.0, half 0.0>)
+ ret <2 x half> %3
+}
+
+define <2 x bfloat> @fma_bf16x2_expanded_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
+; CHECK-LABEL: fma_bf16x2_expanded_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_param_0];
+; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<19>;
+; CHECK-SM70-NEXT: .reg .b32 %r<31>;
+; CHECK-SM70-NEXT: .reg .f32 %f<11>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r15; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r27; }
+; CHECK-SM70-NEXT: and.b32 %r28, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: setp.gt.f32 %p3, %f9, 0f00000000;
+; CHECK-SM70-NEXT: and.b32 %r29, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f10, %r29;
+; CHECK-SM70-NEXT: setp.gt.f32 %p4, %f10, 0f00000000;
+; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p4;
+; CHECK-SM70-NEXT: selp.b16 %rs18, %rs10, 0x0000, %p3;
+; CHECK-SM70-NEXT: mov.b32 %r30, {%rs18, %rs17};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r30;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast <2 x bfloat> %a, %b
+ %2 = fadd fast <2 x bfloat> %1, %c
+ %3 = fcmp ogt <2 x bfloat> %2, <bfloat 0.0, bfloat 0.0>
+ %4 = select <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ ret <2 x bfloat> %4
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define <2 x bfloat> @fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
+; CHECK-LABEL: fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<15>;
+; CHECK-NEXT: .reg .b32 %r<20>;
+; CHECK-NEXT: .reg .f32 %f<11>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: max.bf16x2 %r6, %r4, %r5;
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-NEXT: cvt.u32.u16 %r7, %rs1;
+; CHECK-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-NEXT: mov.b32 %f1, %r8;
+; CHECK-NEXT: add.rn.f32 %f2, %f1, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs4, %f2;
+; CHECK-NEXT: cvt.u32.u16 %r9, %rs2;
+; CHECK-NEXT: shl.b32 %r10, %r9, 16;
+; CHECK-NEXT: mov.b32 %f3, %r10;
+; CHECK-NEXT: add.rn.f32 %f4, %f3, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs6, %f4;
+; CHECK-NEXT: mov.b32 {%rs7, %rs8}, %r6;
+; CHECK-NEXT: cvt.u32.u16 %r11, %rs8;
+; CHECK-NEXT: shl.b32 %r12, %r11, 16;
+; CHECK-NEXT: mov.b32 %f5, %r12;
+; CHECK-NEXT: cvt.u32.u16 %r13, %rs6;
+; CHECK-NEXT: shl.b32 %r14, %r13, 16;
+; CHECK-NEXT: mov.b32 %f6, %r14;
+; CHECK-NEXT: add.rn.f32 %f7, %f5, %f6;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs11, %f7;
+; CHECK-NEXT: cvt.u32.u16 %r15, %rs7;
+; CHECK-NEXT: shl.b32 %r16, %r15, 16;
+; CHECK-NEXT: mov.b32 %f8, %r16;
+; CHECK-NEXT: cvt.u32.u16 %r17, %rs4;
+; CHECK-NEXT: shl.b32 %r18, %r17, 16;
+; CHECK-NEXT: mov.b32 %f9, %r18;
+; CHECK-NEXT: add.rn.f32 %f10, %f8, %f9;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs14, %f10;
+; CHECK-NEXT: mov.b32 %r19, {%rs14, %rs11};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r19;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<15>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<20>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<11>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
+; CHECK-FTZ-NEXT: max.bf16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r7, %rs1;
+; CHECK-FTZ-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r8;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f2, %f1, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs4, %f2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r9, %rs2;
+; CHECK-FTZ-NEXT: shl.b32 %r10, %r9, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f3, %r10;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f4, %f3, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs6, %f4;
+; CHECK-FTZ-NEXT: mov.b32 {%rs7, %rs8}, %r6;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r11, %rs8;
+; CHECK-FTZ-NEXT: shl.b32 %r12, %r11, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f5, %r12;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r13, %rs6;
+; CHECK-FTZ-NEXT: shl.b32 %r14, %r13, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f6, %r14;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f7, %f5, %f6;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs11, %f7;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r15, %rs7;
+; CHECK-FTZ-NEXT: shl.b32 %r16, %r15, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f8, %r16;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r17, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r18, %r17, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f9, %r18;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f10, %f8, %f9;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs14, %f10;
+; CHECK-FTZ-NEXT: mov.b32 %r19, {%rs14, %rs11};
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r19;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<9>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<25>;
+; CHECK-SM70-NEXT: .reg .b32 %r<61>;
+; CHECK-SM70-NEXT: .reg .f32 %f<19>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r15; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r27; }
+; CHECK-SM70-NEXT: and.b32 %r28, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: setp.gt.f32 %p3, %f9, 0f00000000;
+; CHECK-SM70-NEXT: and.b32 %r29, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f10, %r29;
+; CHECK-SM70-NEXT: setp.gt.f32 %p4, %f10, 0f00000000;
+; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p4;
+; CHECK-SM70-NEXT: selp.b16 %rs18, %rs10, 0x0000, %p3;
+; CHECK-SM70-NEXT: add.rn.f32 %f11, %f10, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r30, %f11;
+; CHECK-SM70-NEXT: bfe.u32 %r31, %r30, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r32, %r31, %r30;
+; CHECK-SM70-NEXT: add.s32 %r33, %r32, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p5, %f11, %f11;
+; CHECK-SM70-NEXT: or.b32 %r34, %r30, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r35, %r34, %r33, %p5;
+; CHECK-SM70-NEXT: add.rn.f32 %f12, %f9, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p6, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p6;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r42, %rs18;
+; CHECK-SM70-NEXT: shl.b32 %r43, %r42, 16;
+; CHECK-SM70-NEXT: mov.b32 %f13, %r43;
+; CHECK-SM70-NEXT: and.b32 %r44, %r41, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f14, %r44;
+; CHECK-SM70-NEXT: add.rn.f32 %f15, %f13, %f14;
+; CHECK-SM70-NEXT: mov.b32 %r45, %f15;
+; CHECK-SM70-NEXT: bfe.u32 %r46, %r45, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r47, %r46, %r45;
+; CHECK-SM70-NEXT: add.s32 %r48, %r47, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p7, %f15, %f15;
+; CHECK-SM70-NEXT: or.b32 %r49, %r45, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r50, %r49, %r48, %p7;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs20}, %r50; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r51, %rs17;
+; CHECK-SM70-NEXT: shl.b32 %r52, %r51, 16;
+; CHECK-SM70-NEXT: mov.b32 %f16, %r52;
+; CHECK-SM70-NEXT: and.b32 %r53, %r35, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f17, %r53;
+; CHECK-SM70-NEXT: add.rn.f32 %f18, %f16, %f17;
+; CHECK-SM70-NEXT: mov.b32 %r54, %f18;
+; CHECK-SM70-NEXT: bfe.u32 %r55, %r54, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r56, %r55, %r54;
+; CHECK-SM70-NEXT: add.s32 %r57, %r56, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p8, %f18, %f18;
+; CHECK-SM70-NEXT: or.b32 %r58, %r54, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r59, %r58, %r57, %p8;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs23}, %r59; }
+; CHECK-SM70-NEXT: mov.b32 %r60, {%rs23, %rs20};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r60;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast <2 x bfloat> %a, %b
+ %2 = fadd fast <2 x bfloat> %1, %c
+ %3 = fcmp ogt <2 x bfloat> %2, <bfloat 0.0, bfloat 0.0>
+ %4 = select <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ %5 = fadd <2 x bfloat> %2, <bfloat 7.0, bfloat 7.0>
+ %6 = fadd <2 x bfloat> %4, %5
+ ret <2 x bfloat> %6
+}
+
+define <2 x bfloat> @fma_bf16x2_expanded_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
+; CHECK-LABEL: fma_bf16x2_expanded_maxnum_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_no_nans_param_0];
+; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_expanded_maxnum_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_expanded_maxnum_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
+; CHECK-SM70-NEXT: .reg .b32 %r<43>;
+; CHECK-SM70-NEXT: .reg .f32 %f<13>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_expanded_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_expanded_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: and.b32 %r28, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: max.f32 %f10, %f9, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r29, %f10;
+; CHECK-SM70-NEXT: bfe.u32 %r30, %r29, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r31, %r30, %r29;
+; CHECK-SM70-NEXT: add.s32 %r32, %r31, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f10, %f10;
+; CHECK-SM70-NEXT: or.b32 %r33, %r29, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r34, %r33, %r32, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs13}, %r34; }
+; CHECK-SM70-NEXT: and.b32 %r35, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f11, %r35;
+; CHECK-SM70-NEXT: max.f32 %f12, %f11, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p4;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r41; }
+; CHECK-SM70-NEXT: mov.b32 %r42, {%rs15, %rs13};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r42;
+; CHECK-SM70-NEXT: ret;
+ %1 = fmul fast <2 x bfloat> %a, %b
+ %2 = fadd fast <2 x bfloat> %1, %c
+ %3 = call <2 x bfloat> @llvm.maxnum.bf16x2(<2 x bfloat> %2, <2 x bfloat> <bfloat 0.0, bfloat 0.0>)
+ ret <2 x bfloat> %3
+}
+
+define half @fma_f16_no_nans(half %a, half %b, half %c) {
+; CHECK-LABEL: fma_f16_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan half @llvm.fma.f16(half %a, half %b, half %c)
+ %2 = fcmp ogt half %1, 0.0
+ %3 = select i1 %2, half %1, half 0.0
+ ret half %3
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define half @fma_f16_no_nans_multiple_uses_of_fma(half %a, half %b, half %c) {
+; CHECK-LABEL: fma_f16_no_nans_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: mov.b16 %rs5, 0x4700;
+; CHECK-NEXT: add.rn.f16 %rs6, %rs4, %rs5;
+; CHECK-NEXT: add.rn.f16 %rs7, %rs6, %rs4;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_no_nans_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<8>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: mov.b16 %rs5, 0x4700;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16 %rs6, %rs4, %rs5;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16 %rs7, %rs6, %rs4;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_no_nans_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<8>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: mov.b16 %rs5, 0x4700;
+; CHECK-SM70-NEXT: add.rn.f16 %rs6, %rs4, %rs5;
+; CHECK-SM70-NEXT: add.rn.f16 %rs7, %rs6, %rs4;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan half @llvm.fma.f16(half %a, half %b, half %c)
+ %2 = fcmp ogt half %1, 0.0
+ %3 = select i1 %2, half %1, half 0.0
+ %4 = fadd half %1, 7.0
+ %5 = fadd half %4, %1
+ ret half %5
+}
+
+define half @fma_f16_maxnum_no_nans(half %a, half %b, half %c) {
+; CHECK-LABEL: fma_f16_maxnum_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_no_nans_param_2];
+; CHECK-NEXT: fma.rn.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16_maxnum_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16_maxnum_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<3>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b16 %rs1, [fma_f16_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b16 %rs2, [fma_f16_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b16 %rs3, [fma_f16_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: fma.rn.f16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs4;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %f2;
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan half @llvm.fma.f16(half %a, half %b, half %c)
+ %2 = call half @llvm.maxnum.f16(half %1, half 0.0)
+ ret half %2
+}
+
+define bfloat @fma_bf16_no_nans(bfloat %a, bfloat %b, bfloat %c) {
+; CHECK-LABEL: fma_bf16_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_no_nans_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_no_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_no_nans_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_no_nans_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_no_nans_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
+ %2 = fcmp ogt bfloat %1, 0.0
+ %3 = select i1 %2, bfloat %1, bfloat 0.0
+ ret bfloat %3
+}
+
+; FMA_relu shouldn't be selected if the FMA operation has multiple uses
+define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) {
+; CHECK-LABEL: fma_bf16_no_nans_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<9>;
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: cvt.u32.u16 %r1, %rs4;
+; CHECK-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-NEXT: mov.b32 %f1, %r2;
+; CHECK-NEXT: add.rn.f32 %f2, %f1, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs6, %f2;
+; CHECK-NEXT: cvt.u32.u16 %r3, %rs6;
+; CHECK-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-NEXT: mov.b32 %f3, %r4;
+; CHECK-NEXT: add.rn.f32 %f4, %f3, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs8, %f4;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs8;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_no_nans_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<9>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: fma.rn.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r1, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r2;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f2, %f1, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs6, %f2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r3, %rs6;
+; CHECK-FTZ-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f3, %r4;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f4, %f3, %f1;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs8, %f4;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs8;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_no_nans_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<4>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<27>;
+; CHECK-SM70-NEXT: .reg .f32 %f<9>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: add.rn.f32 %f6, %f5, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: and.b32 %r20, %r19, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r20;
+; CHECK-SM70-NEXT: add.rn.f32 %f8, %f7, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r21, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r22, %r21, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r23, %r22, %r21;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r25, %r21, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r26, %r25, %r24, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r26; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
+ %2 = fcmp ogt bfloat %1, 0.0
+ %3 = select i1 %2, bfloat %1, bfloat 0.0
+ %4 = fadd bfloat %1, 7.0
+ %5 = fadd bfloat %4, %1
+ ret bfloat %5
+}
+
+define bfloat @fma_bf16_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) {
+; CHECK-LABEL: fma_bf16_maxnum_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_no_nans_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_no_nans_param_2];
+; CHECK-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16_maxnum_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b16 %rs1, [fma_bf16_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs2, [fma_bf16_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b16 %rs3, [fma_bf16_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16 %rs4, %rs1, %rs2, %rs3;
+; CHECK-FTZ-NEXT: st.param.b16 [func_retval0], %rs4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16_maxnum_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<3>;
+; CHECK-SM70-NEXT: .reg .b32 %r<20>;
+; CHECK-SM70-NEXT: .reg .f32 %f<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.u16 %r1, [fma_bf16_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: shl.b32 %r2, %r1, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r2;
+; CHECK-SM70-NEXT: ld.param.u16 %r3, [fma_bf16_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: shl.b32 %r4, %r3, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r4;
+; CHECK-SM70-NEXT: ld.param.u16 %r5, [fma_bf16_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r6;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r7, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r8, %r7, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r9, %r8, %r7;
+; CHECK-SM70-NEXT: add.s32 %r10, %r9, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r11, %r7, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r12, %r11, %r10, %p1;
+; CHECK-SM70-NEXT: and.b32 %r13, %r12, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r13;
+; CHECK-SM70-NEXT: max.f32 %f6, %f5, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r14, %f6;
+; CHECK-SM70-NEXT: bfe.u32 %r15, %r14, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r16, %r15, %r14;
+; CHECK-SM70-NEXT: add.s32 %r17, %r16, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f6, %f6;
+; CHECK-SM70-NEXT: or.b32 %r18, %r14, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r19, %r18, %r17, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r19; }
+; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
+ %2 = call bfloat @llvm.maxnum.bf16(bfloat %1, bfloat 0.0)
+ ret bfloat %2
+}
+
+define <2 x half> @fma_f16x2_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
+; CHECK-LABEL: fma_f16x2_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<7>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_param_0];
+; CHECK-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: max.f16x2 %r6, %r4, %r5;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<7>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 0;
+; CHECK-FTZ-NEXT: max.ftz.f16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<3>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<7>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 0;
+; CHECK-SM70-NEXT: setp.gt.f16x2 %p1|%p2, %r4, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: selp.b16 %rs3, %rs2, 0x0000, %p2;
+; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1;
+; CHECK-SM70-NEXT: mov.b32 %r6, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-SM70-NEXT: ret;
+ %1 = call <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c)
+ %2 = fcmp ogt <2 x half> %1, <half 0.0, half 0.0>
+ %3 = select <2 x i1> %2, <2 x half> %1, <2 x half> <half 0.0, half 0.0>
+ ret <2 x half> %3
+}
+
+; FMA relu shouldn't be selected if the FMA operation has multiple uses
+define <2 x half> @fma_f16x2_no_nans_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
+; CHECK-LABEL: fma_f16x2_no_nans_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<8>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 %r5, 1191200512;
+; CHECK-NEXT: add.rn.f16x2 %r6, %r4, %r5;
+; CHECK-NEXT: add.rn.f16x2 %r7, %r6, %r4;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_no_nans_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<8>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 %r5, 1191200512;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16x2 %r6, %r4, %r5;
+; CHECK-FTZ-NEXT: add.rn.ftz.f16x2 %r7, %r6, %r4;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_no_nans_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b32 %r<8>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 %r5, 1191200512;
+; CHECK-SM70-NEXT: add.rn.f16x2 %r6, %r4, %r5;
+; CHECK-SM70-NEXT: add.rn.f16x2 %r7, %r6, %r4;
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c)
+ %2 = fcmp ogt <2 x half> %1, <half 0.0, half 0.0>
+ %3 = select <2 x i1> %2, <2 x half> %1, <2 x half> <half 0.0, half 0.0>
+ %4 = fadd <2 x half> %1, <half 7.0, half 7.0>
+ %5 = fadd <2 x half> %4, %1
+ ret <2 x half> %5
+}
+
+define <2 x half> @fma_f16x2_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
+; CHECK-LABEL: fma_f16x2_maxnum_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_no_nans_param_0];
+; CHECK-NEXT: fma.rn.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_f16x2_maxnum_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.ftz.relu.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_f16x2_maxnum_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .b16 %rs<5>;
+; CHECK-SM70-NEXT: .reg .b32 %r<6>;
+; CHECK-SM70-NEXT: .reg .f32 %f<5>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_f16x2_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_f16x2_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_f16x2_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: fma.rn.f16x2 %r4, %r3, %r2, %r1;
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-SM70-NEXT: max.f32 %f2, %f1, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-SM70-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-SM70-NEXT: max.f32 %f4, %f3, 0f00000000;
+; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-SM70-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c)
+ %2 = call <2 x half> @llvm.maxnum.f16x2(<2 x half> %1, <2 x half> <half 0.0, half 0.0>)
+ ret <2 x half> %2
+}
+
+define <2 x bfloat> @fma_bf16x2_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
+; CHECK-LABEL: fma_bf16x2_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_param_0];
+; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<19>;
+; CHECK-SM70-NEXT: .reg .b32 %r<31>;
+; CHECK-SM70-NEXT: .reg .f32 %f<11>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs10}, %r15; }
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r27; }
+; CHECK-SM70-NEXT: and.b32 %r28, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: setp.gt.f32 %p3, %f9, 0f00000000;
+; CHECK-SM70-NEXT: and.b32 %r29, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f10, %r29;
+; CHECK-SM70-NEXT: setp.gt.f32 %p4, %f10, 0f00000000;
+; CHECK-SM70-NEXT: selp.b16 %rs17, %rs15, 0x0000, %p4;
+; CHECK-SM70-NEXT: selp.b16 %rs18, %rs10, 0x0000, %p3;
+; CHECK-SM70-NEXT: mov.b32 %r30, {%rs18, %rs17};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r30;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
+ %2 = fcmp ogt <2 x bfloat> %1, <bfloat 0.0, bfloat 0.0>
+ %3 = select <2 x i1> %2, <2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ ret <2 x bfloat> %3
+}
+
+; FMA_relu shouldn't be selected if the FMA operation has multiple uses
+define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
+; CHECK-LABEL: fma_bf16x2_no_nans_multiple_uses_of_fma(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<11>;
+; CHECK-NEXT: .reg .b32 %r<14>;
+; CHECK-NEXT: .reg .f32 %f<9>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-NEXT: mov.b32 %f1, %r6;
+; CHECK-NEXT: add.rn.f32 %f2, %f1, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs4, %f2;
+; CHECK-NEXT: cvt.u32.u16 %r7, %rs2;
+; CHECK-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-NEXT: mov.b32 %f3, %r8;
+; CHECK-NEXT: add.rn.f32 %f4, %f3, 0f40E00000;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs6, %f4;
+; CHECK-NEXT: cvt.u32.u16 %r9, %rs6;
+; CHECK-NEXT: shl.b32 %r10, %r9, 16;
+; CHECK-NEXT: mov.b32 %f5, %r10;
+; CHECK-NEXT: add.rn.f32 %f6, %f5, %f3;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs8, %f6;
+; CHECK-NEXT: cvt.u32.u16 %r11, %rs4;
+; CHECK-NEXT: shl.b32 %r12, %r11, 16;
+; CHECK-NEXT: mov.b32 %f7, %r12;
+; CHECK-NEXT: add.rn.f32 %f8, %f7, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs10, %f8;
+; CHECK-NEXT: mov.b32 %r13, {%rs10, %rs8};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_no_nans_multiple_uses_of_fma(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b16 %rs<11>;
+; CHECK-FTZ-NEXT: .reg .b32 %r<14>;
+; CHECK-FTZ-NEXT: .reg .f32 %f<9>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-FTZ-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r5, %rs1;
+; CHECK-FTZ-NEXT: shl.b32 %r6, %r5, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f1, %r6;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f2, %f1, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs4, %f2;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r7, %rs2;
+; CHECK-FTZ-NEXT: shl.b32 %r8, %r7, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f3, %r8;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f4, %f3, 0f40E00000;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs6, %f4;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r9, %rs6;
+; CHECK-FTZ-NEXT: shl.b32 %r10, %r9, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f5, %r10;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f6, %f5, %f3;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs8, %f6;
+; CHECK-FTZ-NEXT: cvt.u32.u16 %r11, %rs4;
+; CHECK-FTZ-NEXT: shl.b32 %r12, %r11, 16;
+; CHECK-FTZ-NEXT: mov.b32 %f7, %r12;
+; CHECK-FTZ-NEXT: add.rn.ftz.f32 %f8, %f7, %f1;
+; CHECK-FTZ-NEXT: cvt.rn.bf16.f32 %rs10, %f8;
+; CHECK-FTZ-NEXT: mov.b32 %r13, {%rs10, %rs8};
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_no_nans_multiple_uses_of_fma(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<7>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
+; CHECK-SM70-NEXT: .reg .b32 %r<57>;
+; CHECK-SM70-NEXT: .reg .f32 %f<17>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: and.b32 %r28, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: add.rn.f32 %f10, %f9, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r29, %f10;
+; CHECK-SM70-NEXT: bfe.u32 %r30, %r29, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r31, %r30, %r29;
+; CHECK-SM70-NEXT: add.s32 %r32, %r31, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f10, %f10;
+; CHECK-SM70-NEXT: or.b32 %r33, %r29, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r34, %r33, %r32, %p3;
+; CHECK-SM70-NEXT: and.b32 %r35, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f11, %r35;
+; CHECK-SM70-NEXT: add.rn.f32 %f12, %f11, 0f40E00000;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p4;
+; CHECK-SM70-NEXT: and.b32 %r42, %r41, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f13, %r42;
+; CHECK-SM70-NEXT: add.rn.f32 %f14, %f13, %f11;
+; CHECK-SM70-NEXT: mov.b32 %r43, %f14;
+; CHECK-SM70-NEXT: bfe.u32 %r44, %r43, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r45, %r44, %r43;
+; CHECK-SM70-NEXT: add.s32 %r46, %r45, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p5, %f14, %f14;
+; CHECK-SM70-NEXT: or.b32 %r47, %r43, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r48, %r47, %r46, %p5;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs13}, %r48; }
+; CHECK-SM70-NEXT: and.b32 %r49, %r34, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f15, %r49;
+; CHECK-SM70-NEXT: add.rn.f32 %f16, %f15, %f9;
+; CHECK-SM70-NEXT: mov.b32 %r50, %f16;
+; CHECK-SM70-NEXT: bfe.u32 %r51, %r50, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r52, %r51, %r50;
+; CHECK-SM70-NEXT: add.s32 %r53, %r52, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p6, %f16, %f16;
+; CHECK-SM70-NEXT: or.b32 %r54, %r50, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r55, %r54, %r53, %p6;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r55; }
+; CHECK-SM70-NEXT: mov.b32 %r56, {%rs15, %rs13};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r56;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
+ %2 = fcmp ogt <2 x bfloat> %1, <bfloat 0.0, bfloat 0.0>
+ %3 = select <2 x i1> %2, <2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0>
+ %4 = fadd <2 x bfloat> %1, <bfloat 7.0, bfloat 7.0>
+ %5 = fadd <2 x bfloat> %4, %1
+ ret <2 x bfloat> %5
+}
+
+define <2 x bfloat> @fma_bf16x2_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
+; CHECK-LABEL: fma_bf16x2_maxnum_no_nans(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_no_nans_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_no_nans_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_no_nans_param_0];
+; CHECK-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+;
+; CHECK-FTZ-LABEL: fma_bf16x2_maxnum_no_nans(
+; CHECK-FTZ: {
+; CHECK-FTZ-NEXT: .reg .b32 %r<5>;
+; CHECK-FTZ-EMPTY:
+; CHECK-FTZ-NEXT: // %bb.0:
+; CHECK-FTZ-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_no_nans_param_2];
+; CHECK-FTZ-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_no_nans_param_1];
+; CHECK-FTZ-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_no_nans_param_0];
+; CHECK-FTZ-NEXT: fma.rn.relu.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-FTZ-NEXT: ret;
+;
+; CHECK-SM70-LABEL: fma_bf16x2_maxnum_no_nans(
+; CHECK-SM70: {
+; CHECK-SM70-NEXT: .reg .pred %p<5>;
+; CHECK-SM70-NEXT: .reg .b16 %rs<17>;
+; CHECK-SM70-NEXT: .reg .b32 %r<43>;
+; CHECK-SM70-NEXT: .reg .f32 %f<13>;
+; CHECK-SM70-EMPTY:
+; CHECK-SM70-NEXT: // %bb.0:
+; CHECK-SM70-NEXT: ld.param.b32 %r1, [fma_bf16x2_maxnum_no_nans_param_0];
+; CHECK-SM70-NEXT: ld.param.b32 %r2, [fma_bf16x2_maxnum_no_nans_param_1];
+; CHECK-SM70-NEXT: ld.param.b32 %r3, [fma_bf16x2_maxnum_no_nans_param_2];
+; CHECK-SM70-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-SM70-NEXT: shl.b32 %r5, %r4, 16;
+; CHECK-SM70-NEXT: mov.b32 %f1, %r5;
+; CHECK-SM70-NEXT: mov.b32 {%rs4, %rs5}, %r2;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r6, %rs4;
+; CHECK-SM70-NEXT: shl.b32 %r7, %r6, 16;
+; CHECK-SM70-NEXT: mov.b32 %f2, %r7;
+; CHECK-SM70-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r8, %rs7;
+; CHECK-SM70-NEXT: shl.b32 %r9, %r8, 16;
+; CHECK-SM70-NEXT: mov.b32 %f3, %r9;
+; CHECK-SM70-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-SM70-NEXT: mov.b32 %r10, %f4;
+; CHECK-SM70-NEXT: bfe.u32 %r11, %r10, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r12, %r11, %r10;
+; CHECK-SM70-NEXT: add.s32 %r13, %r12, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p1, %f4, %f4;
+; CHECK-SM70-NEXT: or.b32 %r14, %r10, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r15, %r14, %r13, %p1;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r16, %rs2;
+; CHECK-SM70-NEXT: shl.b32 %r17, %r16, 16;
+; CHECK-SM70-NEXT: mov.b32 %f5, %r17;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r18, %rs5;
+; CHECK-SM70-NEXT: shl.b32 %r19, %r18, 16;
+; CHECK-SM70-NEXT: mov.b32 %f6, %r19;
+; CHECK-SM70-NEXT: cvt.u32.u16 %r20, %rs8;
+; CHECK-SM70-NEXT: shl.b32 %r21, %r20, 16;
+; CHECK-SM70-NEXT: mov.b32 %f7, %r21;
+; CHECK-SM70-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-SM70-NEXT: mov.b32 %r22, %f8;
+; CHECK-SM70-NEXT: bfe.u32 %r23, %r22, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r24, %r23, %r22;
+; CHECK-SM70-NEXT: add.s32 %r25, %r24, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p2, %f8, %f8;
+; CHECK-SM70-NEXT: or.b32 %r26, %r22, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r27, %r26, %r25, %p2;
+; CHECK-SM70-NEXT: and.b32 %r28, %r27, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f9, %r28;
+; CHECK-SM70-NEXT: max.f32 %f10, %f9, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r29, %f10;
+; CHECK-SM70-NEXT: bfe.u32 %r30, %r29, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r31, %r30, %r29;
+; CHECK-SM70-NEXT: add.s32 %r32, %r31, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p3, %f10, %f10;
+; CHECK-SM70-NEXT: or.b32 %r33, %r29, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r34, %r33, %r32, %p3;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs13}, %r34; }
+; CHECK-SM70-NEXT: and.b32 %r35, %r15, -65536;
+; CHECK-SM70-NEXT: mov.b32 %f11, %r35;
+; CHECK-SM70-NEXT: max.f32 %f12, %f11, 0f00000000;
+; CHECK-SM70-NEXT: mov.b32 %r36, %f12;
+; CHECK-SM70-NEXT: bfe.u32 %r37, %r36, 16, 1;
+; CHECK-SM70-NEXT: add.s32 %r38, %r37, %r36;
+; CHECK-SM70-NEXT: add.s32 %r39, %r38, 32767;
+; CHECK-SM70-NEXT: setp.nan.f32 %p4, %f12, %f12;
+; CHECK-SM70-NEXT: or.b32 %r40, %r36, 4194304;
+; CHECK-SM70-NEXT: selp.b32 %r41, %r40, %r39, %p4;
+; CHECK-SM70-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs15}, %r41; }
+; CHECK-SM70-NEXT: mov.b32 %r42, {%rs15, %rs13};
+; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r42;
+; CHECK-SM70-NEXT: ret;
+ %1 = call nnan <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
+ %2 = call <2 x bfloat> @llvm.maxnum.bf16x2(<2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0>)
+ ret <2 x bfloat> %2
+}
>From b5f8d517ba588373388d2c86c09e8da825a67023 Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Tue, 12 Nov 2024 12:29:54 +0000
Subject: [PATCH 11/14] Refactor instruction defs
Use a multiclass to refactor instruction defs.
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 33 +++++++++----------------
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index e5b0d616ad27eb..ae2f877650d44c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3923,31 +3923,20 @@ def NVPTX_fma_oneuse_and_nnan : PatFrag<(ops node:$a, node:$b, node:$c),
return N->hasOneUse() && N->getFlags().hasNoNaNs();
}]>;
-def FMARELU_F16 :
- NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
- "fma.rn.relu.f16 \t$dst, $a, $b, $c;", []>,
+multiclass FMARELU<RegisterClass RC, string OpVecString = ""> {
+ def _F16# !toupper(OpVecString) : NVPTXInst<(outs RC:$dst), (ins RC:$a, RC:$b, RC:$c),
+ !strconcat("fma.rn.relu.f16", OpVecString, "\t$dst, $a, $b, $c;"), []>,
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
-def FMARELU_BF16 :
- NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
- "fma.rn.relu.bf16 \t$dst, $a, $b, $c;", []>,
- Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
-def FMARELU_F16X2 :
- NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
- "fma.rn.relu.f16x2 \t$dst, $a, $b, $c;", []>,
+ def _F16# !toupper(OpVecString) #_FTZ : NVPTXInst<(outs RC:$dst), (ins RC:$a, RC:$b, RC:$c),
+ !strconcat("fma.rn.ftz.relu.f16", OpVecString, "\t$dst, $a, $b, $c;"), []>,
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
-def FMARELU_BF16X2 :
- NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
- "fma.rn.relu.bf16x2 \t$dst, $a, $b, $c;", []>,
+ def _BF16# !toupper(OpVecString) : NVPTXInst<(outs RC:$dst), (ins RC:$a, RC:$b, RC:$c),
+ !strconcat("fma.rn.relu.bf16", OpVecString, "\t$dst, $a, $b, $c;"), []>,
Requires<[hasBF16Math, hasPTX<70>, hasSM<80>]>;
-// FTZ variants are only supported by fp16, not bf16
-def FMARELU_F16_FTZ :
- NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
- "fma.rn.ftz.relu.f16 \t$dst, $a, $b, $c;", []>,
- Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
-def FMARELU_F16X2_FTZ :
- NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
- "fma.rn.ftz.relu.f16x2 \t$dst, $a, $b, $c;", []>,
- Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
+}
+
+defm FMARELU : FMARELU<Int16Regs>;
+defm FMARELU : FMARELU<Int32Regs, "x2">;
// Don't use function attributes, use instruction flag instead
// FTZ variants are only supported by fp16, not bf16
>From 0e2c73ddd63d93294a630afb9f07e572e78359d8 Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Tue, 12 Nov 2024 13:04:42 +0000
Subject: [PATCH 12/14] Check for func attrs in PatFrag
Instead of adding a flag for noNaNsFPMath, just add the check in the
PatFrag which also checks for single use FMA, as well as instruction
flags.
---
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 5 ----
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 1 -
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 10 -------
llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 1 -
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 30 ++-------------------
5 files changed, 2 insertions(+), 45 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index df2bcd71ce71b1..965ed98630a28d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -85,11 +85,6 @@ bool NVPTXDAGToDAGISel::allowUnsafeFPMath() const {
return TL->allowUnsafeFPMath(*MF);
}
-bool NVPTXDAGToDAGISel::noNaNsFPMath() const {
- const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
- return TL->noNaNsFPMath(*MF);
-}
-
bool NVPTXDAGToDAGISel::doRsqrtOpt() const { return EnableRsqrtOpt; }
/// Select - Select instructions not customized! Used for
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index 0a53c8c3f30b6d..c128c082c29837 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -48,7 +48,6 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
bool useF32FTZ() const;
bool allowFMA() const;
bool allowUnsafeFPMath() const;
- bool noNaNsFPMath() const;
bool doRsqrtOpt() const;
NVPTXScopes Scopes{};
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 46db3fc289f877..a95cba586b8fc3 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -5360,16 +5360,6 @@ bool NVPTXTargetLowering::allowUnsafeFPMath(MachineFunction &MF) const {
return F.getFnAttribute("unsafe-fp-math").getValueAsBool();
}
-bool NVPTXTargetLowering::noNaNsFPMath(MachineFunction &MF) const {
- // Honor TargetOptions flags that explicitly say unsafe math is okay.
- if (MF.getTarget().Options.NoNaNsFPMath)
- return true;
-
- // Allow unsafe math if unsafe-fp-math attribute explicitly says so.
- const Function &F = MF.getFunction();
- return F.getFnAttribute("no-nans-fp-math").getValueAsBool();
-}
-
static bool isConstZero(const SDValue &Operand) {
const auto *Const = dyn_cast<ConstantSDNode>(Operand);
return Const && Const->getZExtValue() == 0;
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
index 5c72e3b3d29cd3..824a659671967a 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -576,7 +576,6 @@ class NVPTXTargetLowering : public TargetLowering {
bool allowFMA(MachineFunction &MF, CodeGenOptLevel OptLevel) const;
bool allowUnsafeFPMath(MachineFunction &MF) const;
- bool noNaNsFPMath(MachineFunction &MF) const;
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
EVT) const override {
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index ae2f877650d44c..b8a99af92b9718 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -152,7 +152,6 @@ def allowFMA : Predicate<"allowFMA()">;
def noFMA : Predicate<"!allowFMA()">;
def allowUnsafeFPMath : Predicate<"allowUnsafeFPMath()">;
def noUnsafeFPMath : Predicate<"!allowUnsafeFPMath()">;
-def noNaNsFPMath : Predicate<"noNaNsFPMath()">;
def do_DIVF32_APPROX : Predicate<"getDivF32Level()==0">;
def do_DIVF32_FULL : Predicate<"getDivF32Level()==1">;
@@ -3912,15 +3911,11 @@ def fpimm_any_zero : FPImmLeaf<fAny, [{
def fpimm_positive_zero_v2f16 : PatFrag<(ops), (v2f16 (bitconvert (i32 0)))>;
def fpimm_positive_zero_v2bf16 : PatFrag<(ops), (v2bf16 (bitconvert (i32 0)))>;
-// Patterns will only be used if FMA has a single use, in order to mitigate register pressure
-def NVPTX_fma_oneuse : PatFrag<(ops node:$a, node:$b, node:$c),
- (fma node:$a, node:$b, node:$c), [{
- return N->hasOneUse();
-}]>;
// We can use the instruction flag nnan instead of relying on a function attribute
def NVPTX_fma_oneuse_and_nnan : PatFrag<(ops node:$a, node:$b, node:$c),
(fma node:$a, node:$b, node:$c), [{
- return N->hasOneUse() && N->getFlags().hasNoNaNs();
+ return N->hasOneUse() &&
+ (N->getFlags().hasNoNaNs() || TM.Options.NoNaNsFPMath);
}]>;
multiclass FMARELU<RegisterClass RC, string OpVecString = ""> {
@@ -3955,24 +3950,3 @@ def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int32Regs:$a, Int32Regs:$b,
(FMARELU_F16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>;
def : Pat<(v2bf16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2bf16)),
(FMARELU_BF16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>;
-
-// Use function attributes for noNaNsFPMath, instead of instruction flag
-def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
- (FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
- Requires<[doF32FTZ, noNaNsFPMath]>;
-def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
- (FMARELU_F16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
- Requires<[doF32FTZ, noNaNsFPMath]>;
-// No FTZ
-def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
- (FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
- Requires<[noNaNsFPMath]>;
-def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
- (FMARELU_BF16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
- Requires<[noNaNsFPMath]>;
-def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
- (FMARELU_F16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
- Requires<[noNaNsFPMath]>;
-def : Pat<(v2bf16 (fmaxnum (NVPTX_fma_oneuse Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2bf16)),
- (FMARELU_BF16X2 Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
- Requires<[noNaNsFPMath]>;
>From a1748cf0c9707199be39df1d7faa4d3179d8e069 Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Tue, 12 Nov 2024 14:03:47 +0000
Subject: [PATCH 13/14] Update comments
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index b8a99af92b9718..3edbcbc9387906 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3911,7 +3911,8 @@ def fpimm_any_zero : FPImmLeaf<fAny, [{
def fpimm_positive_zero_v2f16 : PatFrag<(ops), (v2f16 (bitconvert (i32 0)))>;
def fpimm_positive_zero_v2bf16 : PatFrag<(ops), (v2bf16 (bitconvert (i32 0)))>;
-// We can use the instruction flag nnan instead of relying on a function attribute
+// Perform substitution if fma only has one use, and also if instruction has
+// nnan instruction flag or if the TM has NoNaNsFPMath
def NVPTX_fma_oneuse_and_nnan : PatFrag<(ops node:$a, node:$b, node:$c),
(fma node:$a, node:$b, node:$c), [{
return N->hasOneUse() &&
@@ -3922,6 +3923,7 @@ multiclass FMARELU<RegisterClass RC, string OpVecString = ""> {
def _F16# !toupper(OpVecString) : NVPTXInst<(outs RC:$dst), (ins RC:$a, RC:$b, RC:$c),
!strconcat("fma.rn.relu.f16", OpVecString, "\t$dst, $a, $b, $c;"), []>,
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
+ // FTZ variants are only supported by fp16, not bf16
def _F16# !toupper(OpVecString) #_FTZ : NVPTXInst<(outs RC:$dst), (ins RC:$a, RC:$b, RC:$c),
!strconcat("fma.rn.ftz.relu.f16", OpVecString, "\t$dst, $a, $b, $c;"), []>,
Requires<[useFP16Math, hasPTX<70>, hasSM<80>]>;
@@ -3933,15 +3935,15 @@ multiclass FMARELU<RegisterClass RC, string OpVecString = ""> {
defm FMARELU : FMARELU<Int16Regs>;
defm FMARELU : FMARELU<Int32Regs, "x2">;
-// Don't use function attributes, use instruction flag instead
-// FTZ variants are only supported by fp16, not bf16
+// FTZ
def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
(FMARELU_F16_FTZ Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>,
Requires<[doF32FTZ]>;
def : Pat<(v2f16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int32Regs:$a, Int32Regs:$b, Int32Regs:$c), fpimm_positive_zero_v2f16)),
(FMARELU_F16X2_FTZ Int32Regs:$a, Int32Regs:$b, Int32Regs:$c)>,
Requires<[doF32FTZ]>;
-// No FTZ
+
+// NO FTZ
def : Pat<(f16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
(FMARELU_F16 Int16Regs:$a, Int16Regs:$b, Int16Regs:$c)>;
def : Pat<(bf16 (fmaxnum (NVPTX_fma_oneuse_and_nnan Int16Regs:$a, Int16Regs:$b, Int16Regs:$c), fpimm_any_zero)),
>From 282a1a578ebefbabec1fcb94d2f3ff2a8f8f86ed Mon Sep 17 00:00:00 2001
From: Hugh Delaney <hugh.delaney at codeplay.com>
Date: Wed, 13 Nov 2024 17:26:38 +0000
Subject: [PATCH 14/14] Use imm.isZero instead of isExactly
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 3edbcbc9387906..76845a11e169d4 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -3905,7 +3905,7 @@ def atomic_thread_fence_acq_rel_cta :
Requires<[hasPTX<60>, hasSM<70>]>;
def fpimm_any_zero : FPImmLeaf<fAny, [{
- return Imm.isExactlyValue(+0.0) | Imm.isExactlyValue(-0.0);
+ return Imm.isZero();
}]>;
def fpimm_positive_zero_v2f16 : PatFrag<(ops), (v2f16 (bitconvert (i32 0)))>;
More information about the llvm-commits
mailing list