[llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 13 04:32:25 PST 2024
https://github.com/dlav-sc updated https://github.com/llvm/llvm-project/pull/114227
>From 5a5c5f9a96e994cbbe5fe3aeca3dcade0e58f586 Mon Sep 17 00:00:00 2001
From: Daniil Avdeev <daniil.avdeev at syntacore.com>
Date: Wed, 30 Oct 2024 13:24:21 +0000
Subject: [PATCH 1/4] [RISCV][NFC] refactor CFI emitting
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 208 ++++++++++---------
llvm/lib/Target/RISCV/RISCVFrameLowering.h | 5 +-
2 files changed, 114 insertions(+), 99 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index e0abc2d812ccfc..f3cd02326fb26b 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -27,6 +27,102 @@
using namespace llvm;
+static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
+ return RISCV::VRRegClass.contains(BaseReg) ? 1
+ : RISCV::VRM2RegClass.contains(BaseReg) ? 2
+ : RISCV::VRM4RegClass.contains(BaseReg) ? 4
+ : 8;
+}
+
+static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
+ const Register &Reg) {
+ MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
+ // If it's not a grouped vector register, it doesn't have subregister, so
+ // the base register is just itself.
+ if (BaseReg == RISCV::NoRegister)
+ BaseReg = Reg;
+ return BaseReg;
+}
+
+namespace {
+
+struct CFIRestoreRegisterEmitter {
+ CFIRestoreRegisterEmitter(MachineFunction &, const RISCVSubtarget &) {};
+
+ void emit(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
+ const RISCVInstrInfo &TII, const DebugLoc &DL,
+ const CalleeSavedInfo &CS) const {
+ Register Reg = CS.getReg();
+ unsigned CFIIndex = MF.addFrameInst(
+ MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameDestroy);
+ }
+};
+
+class CFIStoreRegisterEmitter {
+ MachineFrameInfo &MFI;
+
+public:
+ CFIStoreRegisterEmitter(MachineFunction &MF, const RISCVSubtarget &)
+ : MFI{MF.getFrameInfo()} {};
+
+ void emit(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
+ const RISCVInstrInfo &TII, const DebugLoc &DL,
+ const CalleeSavedInfo &CS) const {
+ int FrameIdx = CS.getFrameIdx();
+ int64_t Offset = MFI.getObjectOffset(FrameIdx);
+ Register Reg = CS.getReg();
+ unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
+ nullptr, RI.getDwarfRegNum(Reg, true), Offset));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameSetup);
+ }
+};
+
+class CFIRestoreRVVRegisterEmitter {
+ const llvm::RISCVRegisterInfo *TRI;
+
+public:
+ CFIRestoreRVVRegisterEmitter(MachineFunction &, const RISCVSubtarget &STI)
+ : TRI{STI.getRegisterInfo()} {};
+
+ void emit(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
+ const RISCVInstrInfo &TII, const DebugLoc &DL,
+ const CalleeSavedInfo &CS) const {
+ MCRegister BaseReg = getRVVBaseRegister(*TRI, CS.getReg());
+ unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
+ for (unsigned i = 0; i < NumRegs; ++i) {
+ unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
+ nullptr, RI.getDwarfRegNum(BaseReg + i, true)));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameDestroy);
+ }
+ }
+};
+
+} // namespace
+
+template <typename Emitter>
+void RISCVFrameLowering::emitCFIForCSI(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const SmallVector<CalleeSavedInfo, 8> &CSI) const {
+ MachineFunction *MF = MBB.getParent();
+ const RISCVRegisterInfo *RI = STI.getRegisterInfo();
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ DebugLoc DL = MBB.findDebugLoc(MBBI);
+
+ Emitter E{*MF, STI};
+ for (const auto &CS : CSI)
+ E.emit(*MF, MBB, MBBI, *RI, *TII, DL, CS);
+}
+
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
if (ABI == RISCVABI::ABI_ILP32E)
return Align(4);
@@ -610,16 +706,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
.addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameSetup);
- for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
- int FrameIdx = Entry.getFrameIdx();
- int64_t Offset = MFI.getObjectOffset(FrameIdx);
- Register Reg = Entry.getReg();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
- nullptr, RI->getDwarfRegNum(Reg, true), Offset));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameSetup);
- }
+ emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI,
+ getPushOrLibCallsSavedInfo(MF, CSI));
}
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
@@ -661,16 +749,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
.addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameSetup);
- for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
- int FrameIdx = Entry.getFrameIdx();
- int64_t Offset = MFI.getObjectOffset(FrameIdx);
- Register Reg = Entry.getReg();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
- nullptr, RI->getDwarfRegNum(Reg, true), Offset));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameSetup);
- }
+ emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI,
+ getPushOrLibCallsSavedInfo(MF, CSI));
}
if (StackSize != 0) {
@@ -697,20 +777,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// Iterate over list of callee-saved registers and emit .cfi_offset
// directives.
- for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
- int FrameIdx = Entry.getFrameIdx();
- if (FrameIdx >= 0 &&
- MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
- continue;
-
- int64_t Offset = MFI.getObjectOffset(FrameIdx);
- Register Reg = Entry.getReg();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
- nullptr, RI->getDwarfRegNum(Reg, true), Offset));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameSetup);
- }
+ emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
// Generate new FP.
if (hasFP(MF)) {
@@ -895,7 +962,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
.setMIFlag(MachineInstr::FrameDestroy);
}
- emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
+ emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy,
+ getRVVCalleeSavedInfo(MF, CSI));
}
if (FirstSPAdjustAmount) {
@@ -960,14 +1028,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
}
// Recover callee-saved registers.
- for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
- Register Reg = Entry.getReg();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
- nullptr, RI->getDwarfRegNum(Reg, true)));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameDestroy);
- }
+ emitCFIForCSI<CFIRestoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
bool ApplyPop = RVFI->isPushable(MF) && MBBI != MBB.end() &&
MBBI->getOpcode() == RISCV::CM_POP;
@@ -976,7 +1037,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
// space. Align the stack size down to a multiple of 16. This is needed for
// RVE.
// FIXME: Can we increase the stack size to a multiple of 16 instead?
- uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
+ uint64_t Spimm =
+ std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
MBBI->getOperand(1).setImm(Spimm);
StackSize -= Spimm;
@@ -988,14 +1050,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
if (NextI == MBB.end() || NextI->getOpcode() != RISCV::PseudoRET) {
++MBBI;
- for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
- Register Reg = Entry.getReg();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
- nullptr, RI->getDwarfRegNum(Reg, true)));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameDestroy);
- }
+ emitCFIForCSI<CFIRestoreRegisterEmitter>(
+ MBB, MBBI, getPushOrLibCallsSavedInfo(MF, CSI));
// Update CFA offset. After CM_POP SP should be equal to CFA, so CFA
// offset should be a zero.
@@ -1695,23 +1751,6 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
return true;
}
-static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
- return RISCV::VRRegClass.contains(BaseReg) ? 1
- : RISCV::VRM2RegClass.contains(BaseReg) ? 2
- : RISCV::VRM4RegClass.contains(BaseReg) ? 4
- : 8;
-}
-
-static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
- const Register &Reg) {
- MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
- // If it's not a grouped vector register, it doesn't have subregister, so
- // the base register is just itself.
- if (BaseReg == RISCV::NoRegister)
- BaseReg = Reg;
- return BaseReg;
-}
-
void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
MachineFunction *MF = MBB.getParent();
@@ -1737,39 +1776,14 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
for (auto &CS : RVVCSI) {
// Insert the spill to the stack frame.
int FI = CS.getFrameIdx();
- if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::ScalableVector) {
- MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
- unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
- for (unsigned i = 0; i < NumRegs; ++i) {
- unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
- TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
- BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameSetup);
- }
- }
- }
-}
-
-void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
- MachineFunction *MF = MBB.getParent();
- const MachineFrameInfo &MFI = MF->getFrameInfo();
- const RISCVRegisterInfo *RI = STI.getRegisterInfo();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
- DebugLoc DL = MBB.findDebugLoc(MI);
-
- const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
- for (auto &CS : RVVCSI) {
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
for (unsigned i = 0; i < NumRegs; ++i) {
- unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
- nullptr, RI->getDwarfRegNum(BaseReg + i, true)));
+ unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
+ TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameDestroy);
+ .setMIFlag(MachineInstr::FrameSetup);
}
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
index 04dac7d70ce968..94f0494fa8aafc 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
@@ -91,11 +91,12 @@ class RISCVFrameLowering : public TargetFrameLowering {
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
bool HasFP) const;
- void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI) const;
void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
uint64_t &StackSize, int64_t CFAOffset) const;
+ template <typename Emitter>
+ void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const SmallVector<CalleeSavedInfo, 8> &CSI) const;
std::pair<int64_t, Align>
assignRVVStackObjectOffsets(MachineFunction &MF) const;
>From 80c66c52b01ff3e8029ff3df9ba4593d3898a99d Mon Sep 17 00:00:00 2001
From: Daniil Avdeev <daniil.avdeev at syntacore.com>
Date: Wed, 13 Nov 2024 10:26:21 +0000
Subject: [PATCH 2/4] [RISCV][NFC] refactoring
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 155 ++++++++++---------
llvm/lib/Target/RISCV/RISCVFrameLowering.h | 8 +-
2 files changed, 83 insertions(+), 80 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index f3cd02326fb26b..fbb87baeb1bd35 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -27,56 +27,23 @@
using namespace llvm;
-static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
- return RISCV::VRRegClass.contains(BaseReg) ? 1
- : RISCV::VRM2RegClass.contains(BaseReg) ? 2
- : RISCV::VRM4RegClass.contains(BaseReg) ? 4
- : 8;
-}
-
-static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
- const Register &Reg) {
- MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
- // If it's not a grouped vector register, it doesn't have subregister, so
- // the base register is just itself.
- if (BaseReg == RISCV::NoRegister)
- BaseReg = Reg;
- return BaseReg;
-}
-
namespace {
-struct CFIRestoreRegisterEmitter {
- CFIRestoreRegisterEmitter(MachineFunction &, const RISCVSubtarget &) {};
-
- void emit(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
- const RISCVInstrInfo &TII, const DebugLoc &DL,
- const CalleeSavedInfo &CS) const {
- Register Reg = CS.getReg();
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameDestroy);
- }
-};
-
-class CFIStoreRegisterEmitter {
- MachineFrameInfo &MFI;
+class CFISaveRegisterEmitter {
+ MachineFunction &m_MF;
+ MachineFrameInfo &m_MFI;
public:
- CFIStoreRegisterEmitter(MachineFunction &MF, const RISCVSubtarget &)
- : MFI{MF.getFrameInfo()} {};
+ CFISaveRegisterEmitter(MachineFunction &MF)
+ : m_MF{MF}, m_MFI{MF.getFrameInfo()} {};
- void emit(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
- const RISCVInstrInfo &TII, const DebugLoc &DL,
- const CalleeSavedInfo &CS) const {
+ void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
+ const DebugLoc &DL, const CalleeSavedInfo &CS) const {
int FrameIdx = CS.getFrameIdx();
- int64_t Offset = MFI.getObjectOffset(FrameIdx);
+ int64_t Offset = m_MFI.getObjectOffset(FrameIdx);
Register Reg = CS.getReg();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
+ unsigned CFIIndex = m_MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, RI.getDwarfRegNum(Reg, true), Offset));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex)
@@ -84,26 +51,21 @@ class CFIStoreRegisterEmitter {
}
};
-class CFIRestoreRVVRegisterEmitter {
- const llvm::RISCVRegisterInfo *TRI;
+class CFIRestoreRegisterEmitter {
+ MachineFunction &m_MF;
public:
- CFIRestoreRVVRegisterEmitter(MachineFunction &, const RISCVSubtarget &STI)
- : TRI{STI.getRegisterInfo()} {};
-
- void emit(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
- const RISCVInstrInfo &TII, const DebugLoc &DL,
- const CalleeSavedInfo &CS) const {
- MCRegister BaseReg = getRVVBaseRegister(*TRI, CS.getReg());
- unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
- for (unsigned i = 0; i < NumRegs; ++i) {
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
- nullptr, RI.getDwarfRegNum(BaseReg + i, true)));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameDestroy);
- }
+ CFIRestoreRegisterEmitter(MachineFunction &MF) : m_MF{MF} {};
+
+ void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
+ const DebugLoc &DL, const CalleeSavedInfo &CS) const {
+ Register Reg = CS.getReg();
+ unsigned CFIIndex = m_MF.addFrameInst(
+ MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameDestroy);
}
};
@@ -118,9 +80,9 @@ void RISCVFrameLowering::emitCFIForCSI(
const RISCVInstrInfo *TII = STI.getInstrInfo();
DebugLoc DL = MBB.findDebugLoc(MBBI);
- Emitter E{*MF, STI};
+ Emitter E{*MF};
for (const auto &CS : CSI)
- E.emit(*MF, MBB, MBBI, *RI, *TII, DL, CS);
+ E.emit(MBB, MBBI, *RI, *TII, DL, CS);
}
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
@@ -514,18 +476,18 @@ getPushOrLibCallsSavedInfo(const MachineFunction &MF,
const std::vector<CalleeSavedInfo> &CSI) {
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
- SmallVector<CalleeSavedInfo, 8> PushPopOrLibCallsCSI;
+ SmallVector<CalleeSavedInfo, 8> PushOrLibCallsCSI;
if (!RVFI->useSaveRestoreLibCalls(MF) && !RVFI->isPushable(MF))
- return PushPopOrLibCallsCSI;
+ return PushOrLibCallsCSI;
- for (auto &CS : CSI) {
+ for (const auto &CS : CSI) {
const auto *FII = llvm::find_if(
FixedCSRFIMap, [&](auto P) { return P.first == CS.getReg(); });
if (FII != std::end(FixedCSRFIMap))
- PushPopOrLibCallsCSI.push_back(CS);
+ PushOrLibCallsCSI.push_back(CS);
}
- return PushPopOrLibCallsCSI;
+ return PushOrLibCallsCSI;
}
void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
@@ -706,8 +668,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
.addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameSetup);
- emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI,
- getPushOrLibCallsSavedInfo(MF, CSI));
+ emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI,
+ getPushOrLibCallsSavedInfo(MF, CSI));
}
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
@@ -739,7 +701,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// stack space. Align the stack size down to a multiple of 16. This is
// needed for RVE.
// FIXME: Can we increase the stack size to a multiple of 16 instead?
- uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
+ uint64_t Spimm = std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
FirstFrameSetup->getOperand(1).setImm(Spimm);
StackSize -= Spimm;
@@ -749,8 +711,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
.addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameSetup);
- emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI,
- getPushOrLibCallsSavedInfo(MF, CSI));
+ emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI,
+ getPushOrLibCallsSavedInfo(MF, CSI));
}
if (StackSize != 0) {
@@ -777,7 +739,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// Iterate over list of callee-saved registers and emit .cfi_offset
// directives.
- emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
+ emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
// Generate new FP.
if (hasFP(MF)) {
@@ -962,8 +924,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
.setMIFlag(MachineInstr::FrameDestroy);
}
- emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy,
- getRVVCalleeSavedInfo(MF, CSI));
+ emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
}
if (FirstSPAdjustAmount) {
@@ -1751,6 +1712,23 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
return true;
}
+static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg) {
+ return RISCV::VRRegClass.contains(BaseReg) ? 1
+ : RISCV::VRM2RegClass.contains(BaseReg) ? 2
+ : RISCV::VRM4RegClass.contains(BaseReg) ? 4
+ : 8;
+}
+
+static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
+ const Register &Reg) {
+ MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
+ // If it's not a grouped vector register, it doesn't have subregister, so
+ // the base register is just itself.
+ if (BaseReg == RISCV::NoRegister)
+ BaseReg = Reg;
+ return BaseReg;
+}
+
void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
MachineFunction *MF = MBB.getParent();
@@ -1777,7 +1755,7 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
// Insert the spill to the stack frame.
int FI = CS.getFrameIdx();
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
- unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
+ unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
for (unsigned i = 0; i < NumRegs; ++i) {
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
@@ -1788,6 +1766,29 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
}
}
+void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
+ MachineFunction *MF = MBB.getParent();
+ const MachineFrameInfo &MFI = MF->getFrameInfo();
+ const RISCVRegisterInfo *RI = STI.getRegisterInfo();
+ const TargetInstrInfo &TII = *STI.getInstrInfo();
+ const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
+ DebugLoc DL = MBB.findDebugLoc(MI);
+
+ const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
+ for (auto &CS : RVVCSI) {
+ MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
+ unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
+ for (unsigned i = 0; i < NumRegs; ++i) {
+ unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
+ nullptr, RI->getDwarfRegNum(BaseReg + i, true)));
+ BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameDestroy);
+ }
+ }
+}
+
bool RISCVFrameLowering::restoreCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
index 94f0494fa8aafc..c106b7b6754653 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
@@ -91,12 +91,14 @@ class RISCVFrameLowering : public TargetFrameLowering {
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
bool HasFP) const;
- void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
- uint64_t &StackSize, int64_t CFAOffset) const;
+ void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const;
template <typename Emitter>
void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const SmallVector<CalleeSavedInfo, 8> &CSI) const;
+ void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
+ uint64_t &StackSize, int64_t CFAOffset) const;
std::pair<int64_t, Align>
assignRVVStackObjectOffsets(MachineFunction &MF) const;
>From 081ab881f4f84040d18536e3bfd2142fa1f7c1d2 Mon Sep 17 00:00:00 2001
From: Daniil Avdeev <daniil.avdeev at syntacore.com>
Date: Wed, 13 Nov 2024 12:20:27 +0000
Subject: [PATCH 3/4] [RISCV][NFC] rvv refactoring
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 276 +++++++++----------
llvm/lib/Target/RISCV/RISCVFrameLowering.h | 5 -
2 files changed, 138 insertions(+), 143 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index fbb87baeb1bd35..66eeab1bfa6e95 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -27,64 +27,6 @@
using namespace llvm;
-namespace {
-
-class CFISaveRegisterEmitter {
- MachineFunction &m_MF;
- MachineFrameInfo &m_MFI;
-
-public:
- CFISaveRegisterEmitter(MachineFunction &MF)
- : m_MF{MF}, m_MFI{MF.getFrameInfo()} {};
-
- void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
- const DebugLoc &DL, const CalleeSavedInfo &CS) const {
- int FrameIdx = CS.getFrameIdx();
- int64_t Offset = m_MFI.getObjectOffset(FrameIdx);
- Register Reg = CS.getReg();
- unsigned CFIIndex = m_MF.addFrameInst(MCCFIInstruction::createOffset(
- nullptr, RI.getDwarfRegNum(Reg, true), Offset));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameSetup);
- }
-};
-
-class CFIRestoreRegisterEmitter {
- MachineFunction &m_MF;
-
-public:
- CFIRestoreRegisterEmitter(MachineFunction &MF) : m_MF{MF} {};
-
- void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
- const DebugLoc &DL, const CalleeSavedInfo &CS) const {
- Register Reg = CS.getReg();
- unsigned CFIIndex = m_MF.addFrameInst(
- MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameDestroy);
- }
-};
-
-} // namespace
-
-template <typename Emitter>
-void RISCVFrameLowering::emitCFIForCSI(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const SmallVector<CalleeSavedInfo, 8> &CSI) const {
- MachineFunction *MF = MBB.getParent();
- const RISCVRegisterInfo *RI = STI.getRegisterInfo();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
- DebugLoc DL = MBB.findDebugLoc(MBBI);
-
- Emitter E{*MF};
- for (const auto &CS : CSI)
- E.emit(MBB, MBBI, *RI, *TII, DL, CS);
-}
-
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
if (ABI == RISCVABI::ABI_ILP32E)
return Align(4);
@@ -602,6 +544,142 @@ static MCCFIInstruction createDefCFAOffset(const TargetRegisterInfo &TRI,
Comment.str());
}
+static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg) {
+ return RISCV::VRRegClass.contains(BaseReg) ? 1
+ : RISCV::VRM2RegClass.contains(BaseReg) ? 2
+ : RISCV::VRM4RegClass.contains(BaseReg) ? 4
+ : 8;
+}
+
+static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
+ const Register &Reg) {
+ MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
+ // If it's not a grouped vector register, it doesn't have subregister, so
+ // the base register is just itself.
+ if (BaseReg == RISCV::NoRegister)
+ BaseReg = Reg;
+ return BaseReg;
+}
+
+namespace {
+
+class CFISaveRegisterEmitter {
+ MachineFunction &m_MF;
+ MachineFrameInfo &m_MFI;
+
+public:
+ CFISaveRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF)
+ : m_MF{MF}, m_MFI{MF.getFrameInfo()} {};
+
+ void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
+ const DebugLoc &DL, const CalleeSavedInfo &CS) const {
+ int FrameIdx = CS.getFrameIdx();
+ int64_t Offset = m_MFI.getObjectOffset(FrameIdx);
+ Register Reg = CS.getReg();
+ unsigned CFIIndex = m_MF.addFrameInst(MCCFIInstruction::createOffset(
+ nullptr, RI.getDwarfRegNum(Reg, true), Offset));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameSetup);
+ }
+};
+
+class CFIRestoreRegisterEmitter {
+ MachineFunction &m_MF;
+
+public:
+ CFIRestoreRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF) : m_MF{MF} {};
+
+ void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
+ const DebugLoc &DL, const CalleeSavedInfo &CS) const {
+ Register Reg = CS.getReg();
+ unsigned CFIIndex = m_MF.addFrameInst(
+ MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameDestroy);
+ }
+};
+
+class CFISaveRVVRegisterEmitter {
+ MachineFunction &m_MF;
+ MachineFrameInfo &m_MFI;
+ const uint64_t m_FixedSize;
+
+ static uint64_t getFixedSize(const RISCVFrameLowering &FL, MachineFunction &MF, MachineFrameInfo &MFI) {
+ const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+
+ uint64_t FixedSize = FL.getStackSizeWithRVVPadding(MF);
+ if (!FL.hasFP(MF)) {
+ uint64_t ScalarLocalVarSize =
+ MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
+ RVFI->getRVPushStackSize() - RVFI->getVarArgsSaveSize() +
+ RVFI->getRVVPadding();
+ FixedSize -= ScalarLocalVarSize;
+ }
+ return FixedSize;
+ }
+
+public:
+ CFISaveRVVRegisterEmitter(const RISCVFrameLowering &FL, MachineFunction &MF) : m_MF{MF}, m_MFI{MF.getFrameInfo()}, m_FixedSize{getFixedSize(FL, MF, m_MFI)} {};
+
+void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
+ const DebugLoc &DL, const CalleeSavedInfo &CS) const {
+
+ // Insert the spill to the stack frame.
+ int FI = CS.getFrameIdx();
+ MCRegister BaseReg = getRVVBaseRegister(RI, CS.getReg());
+ unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
+ for (unsigned i = 0; i < NumRegs; ++i) {
+ unsigned CFIIndex = m_MF.addFrameInst(createDefCFAOffset(
+ RI, BaseReg + i, -m_FixedSize, m_MFI.getObjectOffset(FI) / 8 + i));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameSetup);
+ }
+ }
+};
+
+class CFIRestoreRVVRegisterEmitter {
+ MachineFunction &m_MF;
+
+public:
+ CFIRestoreRVVRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF) : m_MF{MF} {};
+
+void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
+ const DebugLoc &DL, const CalleeSavedInfo &CS) const {
+ MCRegister BaseReg = getRVVBaseRegister(RI, CS.getReg());
+ unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
+ for (unsigned i = 0; i < NumRegs; ++i) {
+ unsigned CFIIndex = m_MF.addFrameInst(MCCFIInstruction::createRestore(
+ nullptr, RI.getDwarfRegNum(BaseReg + i, true)));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameDestroy);
+ }
+ }
+};
+
+} // namespace
+
+template <typename Emitter>
+void RISCVFrameLowering::emitCFIForCSI(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const SmallVector<CalleeSavedInfo, 8> &CSI) const {
+ MachineFunction *MF = MBB.getParent();
+ const RISCVRegisterInfo *RI = STI.getRegisterInfo();
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ DebugLoc DL = MBB.findDebugLoc(MBBI);
+
+ Emitter E{*this, *MF};
+ for (const auto &CS : CSI)
+ E.emit(MBB, MBBI, *RI, *TII, DL, CS);
+}
+
void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -796,7 +874,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
}
std::advance(MBBI, getRVVCalleeSavedInfo(MF, CSI).size());
- emitCalleeSavedRVVPrologCFI(MBB, MBBI, hasFP(MF));
+ emitCFIForCSI<CFISaveRVVRegisterEmitter>(MBB, MBBI, getRVVCalleeSavedInfo(MF, CSI));
}
if (hasFP(MF)) {
@@ -923,8 +1001,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
.addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameDestroy);
}
-
- emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
+ emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy, getRVVCalleeSavedInfo(MF, CSI));
}
if (FirstSPAdjustAmount) {
@@ -1712,83 +1789,6 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
return true;
}
-static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg) {
- return RISCV::VRRegClass.contains(BaseReg) ? 1
- : RISCV::VRM2RegClass.contains(BaseReg) ? 2
- : RISCV::VRM4RegClass.contains(BaseReg) ? 4
- : 8;
-}
-
-static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
- const Register &Reg) {
- MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
- // If it's not a grouped vector register, it doesn't have subregister, so
- // the base register is just itself.
- if (BaseReg == RISCV::NoRegister)
- BaseReg = Reg;
- return BaseReg;
-}
-
-void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
- MachineFunction *MF = MBB.getParent();
- const MachineFrameInfo &MFI = MF->getFrameInfo();
- RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
- DebugLoc DL = MBB.findDebugLoc(MI);
-
- const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
- if (RVVCSI.empty())
- return;
-
- uint64_t FixedSize = getStackSizeWithRVVPadding(*MF);
- if (!HasFP) {
- uint64_t ScalarLocalVarSize =
- MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
- RVFI->getRVPushStackSize() - RVFI->getVarArgsSaveSize() +
- RVFI->getRVVPadding();
- FixedSize -= ScalarLocalVarSize;
- }
-
- for (auto &CS : RVVCSI) {
- // Insert the spill to the stack frame.
- int FI = CS.getFrameIdx();
- MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
- unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
- for (unsigned i = 0; i < NumRegs; ++i) {
- unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
- TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
- BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameSetup);
- }
- }
-}
-
-void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
- MachineFunction *MF = MBB.getParent();
- const MachineFrameInfo &MFI = MF->getFrameInfo();
- const RISCVRegisterInfo *RI = STI.getRegisterInfo();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
- DebugLoc DL = MBB.findDebugLoc(MI);
-
- const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
- for (auto &CS : RVVCSI) {
- MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
- unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
- for (unsigned i = 0; i < NumRegs; ++i) {
- unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
- nullptr, RI->getDwarfRegNum(BaseReg + i, true)));
- BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameDestroy);
- }
- }
-}
-
bool RISCVFrameLowering::restoreCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
index c106b7b6754653..9f85b641759185 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
@@ -88,11 +88,6 @@ class RISCVFrameLowering : public TargetFrameLowering {
void adjustStackForRVV(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
int64_t Amount, MachineInstr::MIFlag Flag) const;
- void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- bool HasFP) const;
- void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI) const;
template <typename Emitter>
void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const SmallVector<CalleeSavedInfo, 8> &CSI) const;
>From f29e0f430adc35f3df18ff3de1ee2fa3ce030a6f Mon Sep 17 00:00:00 2001
From: Daniil Avdeev <daniil.avdeev at syntacore.com>
Date: Wed, 13 Nov 2024 12:31:45 +0000
Subject: [PATCH 4/4] format
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 64 +++++++++++---------
1 file changed, 36 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 66eeab1bfa6e95..36521e56cff1de 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -589,7 +589,8 @@ class CFIRestoreRegisterEmitter {
MachineFunction &m_MF;
public:
- CFIRestoreRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF) : m_MF{MF} {};
+ CFIRestoreRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF)
+ : m_MF{MF} {};
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
@@ -606,30 +607,33 @@ class CFIRestoreRegisterEmitter {
class CFISaveRVVRegisterEmitter {
MachineFunction &m_MF;
MachineFrameInfo &m_MFI;
- const uint64_t m_FixedSize;
-
- static uint64_t getFixedSize(const RISCVFrameLowering &FL, MachineFunction &MF, MachineFrameInfo &MFI) {
- const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
-
- uint64_t FixedSize = FL.getStackSizeWithRVVPadding(MF);
- if (!FL.hasFP(MF)) {
- uint64_t ScalarLocalVarSize =
- MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
- RVFI->getRVPushStackSize() - RVFI->getVarArgsSaveSize() +
- RVFI->getRVVPadding();
- FixedSize -= ScalarLocalVarSize;
- }
- return FixedSize;
- }
+ const uint64_t m_FixedSize;
+
+ static uint64_t getFixedSize(const RISCVFrameLowering &FL,
+ MachineFunction &MF, MachineFrameInfo &MFI) {
+ const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+
+ uint64_t FixedSize = FL.getStackSizeWithRVVPadding(MF);
+ if (!FL.hasFP(MF)) {
+ uint64_t ScalarLocalVarSize =
+ MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
+ RVFI->getRVPushStackSize() - RVFI->getVarArgsSaveSize() +
+ RVFI->getRVVPadding();
+ FixedSize -= ScalarLocalVarSize;
+ }
+ return FixedSize;
+ }
public:
- CFISaveRVVRegisterEmitter(const RISCVFrameLowering &FL, MachineFunction &MF) : m_MF{MF}, m_MFI{MF.getFrameInfo()}, m_FixedSize{getFixedSize(FL, MF, m_MFI)} {};
+ CFISaveRVVRegisterEmitter(const RISCVFrameLowering &FL, MachineFunction &MF)
+ : m_MF{MF}, m_MFI{MF.getFrameInfo()},
+ m_FixedSize{getFixedSize(FL, MF, m_MFI)} {};
-void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
- const DebugLoc &DL, const CalleeSavedInfo &CS) const {
+ void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
+ const DebugLoc &DL, const CalleeSavedInfo &CS) const {
- // Insert the spill to the stack frame.
+ // Insert the spill to the stack frame.
int FI = CS.getFrameIdx();
MCRegister BaseReg = getRVVBaseRegister(RI, CS.getReg());
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
@@ -647,11 +651,12 @@ class CFIRestoreRVVRegisterEmitter {
MachineFunction &m_MF;
public:
- CFIRestoreRVVRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF) : m_MF{MF} {};
+ CFIRestoreRVVRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF)
+ : m_MF{MF} {};
-void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
- const DebugLoc &DL, const CalleeSavedInfo &CS) const {
+ void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
+ const DebugLoc &DL, const CalleeSavedInfo &CS) const {
MCRegister BaseReg = getRVVBaseRegister(RI, CS.getReg());
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
for (unsigned i = 0; i < NumRegs; ++i) {
@@ -779,7 +784,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// stack space. Align the stack size down to a multiple of 16. This is
// needed for RVE.
// FIXME: Can we increase the stack size to a multiple of 16 instead?
- uint64_t Spimm = std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
+ uint64_t Spimm =
+ std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
FirstFrameSetup->getOperand(1).setImm(Spimm);
StackSize -= Spimm;
@@ -874,7 +880,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
}
std::advance(MBBI, getRVVCalleeSavedInfo(MF, CSI).size());
- emitCFIForCSI<CFISaveRVVRegisterEmitter>(MBB, MBBI, getRVVCalleeSavedInfo(MF, CSI));
+ emitCFIForCSI<CFISaveRVVRegisterEmitter>(MBB, MBBI,
+ getRVVCalleeSavedInfo(MF, CSI));
}
if (hasFP(MF)) {
@@ -1001,7 +1008,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
.addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameDestroy);
}
- emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy, getRVVCalleeSavedInfo(MF, CSI));
+ emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy,
+ getRVVCalleeSavedInfo(MF, CSI));
}
if (FirstSPAdjustAmount) {
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