[llvm] [AArch64][SVE] Add AArch64ISD nodes for wide add instructions (PR #115895)

[Benjamin Maxwell via llvm-commits]

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@@ -3674,10 +3690,10 @@ let Predicates = [HasSVE2orSME] in {
   defm UABDLT_ZZZ : sve2_wide_int_arith_long<0b01111, "uabdlt", int_aarch64_sve_uabdlt>;
 
   // SVE2 integer add/subtract wide
-  defm SADDWB_ZZZ : sve2_wide_int_arith_wide<0b000, "saddwb", int_aarch64_sve_saddwb>;
-  defm SADDWT_ZZZ : sve2_wide_int_arith_wide<0b001, "saddwt", int_aarch64_sve_saddwt>;
-  defm UADDWB_ZZZ : sve2_wide_int_arith_wide<0b010, "uaddwb", int_aarch64_sve_uaddwb>;
-  defm UADDWT_ZZZ : sve2_wide_int_arith_wide<0b011, "uaddwt", int_aarch64_sve_uaddwt>;
+  defm SADDWB_ZZZ : sve2_wide_int_arith_wide<0b000, "saddwb", AArch64saddwb>;
+  defm SADDWT_ZZZ : sve2_wide_int_arith_wide<0b001, "saddwt", AArch64saddwt>;
+  defm UADDWB_ZZZ : sve2_wide_int_arith_wide<0b010, "uaddwb", AArch64uaddwb>;
+  defm UADDWT_ZZZ : sve2_wide_int_arith_wide<0b011, "uaddwt", AArch64uaddwt>;
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MacDue wrote:

Another option (other than `performIntrinsicCombine()`) for matching the intrinsics could be to add another parameter to `sve2_wide_int_arith_wide` for the intrinsic pattern fragment so that both patterns can be registered here. I've seen this done in `sve_fp_2op_p_zd` (for example). I'm not requesting a change here; I just thought I'd mention this as I've seen it done a few times. 
 

https://github.com/llvm/llvm-project/pull/115895