[llvm] [RISCV] Enable bidirectional postra scheduling (PR #115864)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> How are we evaluating this change? On spills? On impact to dynamic IC? On impact to runtime on real hardware?

IIUC, PostRA scheduling basically won't impact on spills and dynamic instruction count. I will show some cycles/IPC based on GEM5.
I do agree this should be tuned by CPUs, I will make it a tuning feature later but we still need a default setting (`topdown`, `buttomup` or `bidirectional`, this can be debated).

https://github.com/llvm/llvm-project/pull/115864