[llvm] [RISC-V] Lower priority of X5(LR) during regalloc (PR #115867)

[Craig Topper via llvm-commits]

topperc wrote:

This appears to be just the priority for hinting towards compressible instructions? Do you have any numbers on how much additional outlining this gives?

Do we also need to move X5 later in the allocation order in the definition of the GPR register class in RISCVRegisterInfo.td?

https://github.com/llvm/llvm-project/pull/115867