[llvm] [RISCV] Add testcase for return address signing for outlined functions (PR #115079)

[via llvm-commits]

https://github.com/hiraditya updated https://github.com/llvm/llvm-project/pull/115079

>From 7853ce1915f4f24080bb859a2328878f1d6f392c Mon Sep 17 00:00:00 2001
From: AdityaK <hiraditya at msn.com>
Date: Tue, 5 Nov 2024 13:20:58 -0800
Subject: [PATCH] Add testcase for return address signing for outlined
 functions

Adapted from: AArch64/machine-outliner-retaddr-sign-non-leaf.ll
---
 .../machine-outliner-retaddr-sign-non-leaf.ll | 91 +++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/machine-outliner-retaddr-sign-non-leaf.ll

diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-retaddr-sign-non-leaf.ll b/llvm/test/CodeGen/RISCV/machine-outliner-retaddr-sign-non-leaf.ll
new file mode 100644
index 00000000000000..963dd33c5f90a6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-retaddr-sign-non-leaf.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple riscv64 %s -o - | FileCheck %s
+
+define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
+; CHECK-LABEL: a:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mv t5, a0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, ptr %1, align 4
+  store i32 2, ptr %2, align 4
+  store i32 3, ptr %3, align 4
+  store i32 4, ptr %4, align 4
+  store i32 5, ptr %5, align 4
+  store i32 6, ptr %6, align 4
+  call void asm sideeffect "mv x30, $0", "r,~{lr}"(i64 %x) #1
+  ret i64 %x
+}
+
+define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
+; CHECK-LABEL: b:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mv t5, a0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, ptr %1, align 4
+  store i32 2, ptr %2, align 4
+  store i32 3, ptr %3, align 4
+  store i32 4, ptr %4, align 4
+  store i32 5, ptr %5, align 4
+  store i32 6, ptr %6, align 4
+  call void asm sideeffect "mv x30, $0", "r,~{lr}"(i64 %x) #1
+  ret i64 %x
+}
+
+define i64 @c(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
+; CHECK-LABEL: c:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mv t5, a0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, ptr %1, align 4
+  store i32 2, ptr %2, align 4
+  store i32 3, ptr %3, align 4
+  store i32 4, ptr %4, align 4
+  store i32 5, ptr %5, align 4
+  store i32 6, ptr %6, align 4
+  call void asm sideeffect "mv x30, $0", "r,~{lr}"(i64 %x) #1
+  ret i64 %x
+}
+
+;; Outlined function is leaf-function => don't sign it
+; CHECK-LABEL:      OUTLINED_FUNCTION_0:
+; CHECK-NOT:            .cfi_b_key_frame
+; CHECK-NOT:            paci{{[a,b]}}sp
+; CHECK-NOT:            hint #2{{[5,7]}}
+; CHECK-NOT:            .cfi_negate_ra_state
+; CHECK-NOT:            auti{{[a,b]}}sp