[llvm] [PowerPC] Use setbc for values from vector compare conditions (PR #114858)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 12 11:58:46 PST 2024
github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff 7792dbe29a07bd7608281f11b01b8e729f3c9594 1da11ad85ce1de06d36aff9b9df8b063dc906c00 --extensions cpp,h -- llvm/lib/Target/PowerPC/PPCISelLowering.cpp llvm/lib/Target/PowerPC/PPCISelLowering.h
``````````
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d93d0fcdf4..259ee3aab2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11307,15 +11307,15 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SDValue CR6Reg = DAG.getRegister(PPC::CR6, MVT::i32);
SDValue CRBit =
SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::i1,
- CR6Reg, SubRegIdx, GlueOp), 0);
+ CR6Reg, SubRegIdx, GlueOp),
+ 0);
return DAG.getNode(SetOp, dl, MVT::i32, CRBit);
}
// Now that we have the comparison, emit a copy from the CR to a GPR.
// This is flagged to the above dot comparison.
- SDValue Flags =
- DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
- DAG.getRegister(PPC::CR6, MVT::i32), GlueOp);
+ SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
+ DAG.getRegister(PPC::CR6, MVT::i32), GlueOp);
// Shift the bit into the low position.
Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
``````````
</details>
https://github.com/llvm/llvm-project/pull/114858
More information about the llvm-commits
mailing list