[llvm] 5a09424 - [LangRef] Clarify RISC-V v? constraints

[via llvm-commits]

Author: Fangrui Song
Date: 2024-11-12T09:20:54-08:00
New Revision: 5a094241de42867c35611b0eec6f3e19d8718c22

URL: https://github.com/llvm/llvm-project/commit/5a094241de42867c35611b0eec6f3e19d8718c22
DIFF: https://github.com/llvm/llvm-project/commit/5a094241de42867c35611b0eec6f3e19d8718c22.diff

LOG: [LangRef] Clarify RISC-V v? constraints

Pull Request: https://github.com/llvm/llvm-project/pull/115820

Added: 
    

Modified: 
    llvm/docs/LangRef.rst

Removed: 
    


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diff  --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index ef38c5ab33b926..8492b745603410 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -5521,8 +5521,9 @@ RISC-V:
 - ``r``: A 32- or 64-bit general-purpose register (depending on the platform
   ``XLEN``).
 - ``S``: Alias for ``s``.
-- ``vr``: A vector register. (requires V extension).
-- ``vm``: A vector register for masking operand. (requires V extension).
+- ``vd``: A vector register, excluding ``v0`` (requires V extension).
+- ``vm``: The vector register ``v0`` (requires V extension).
+- ``vr``: A vector register (requires V extension).
 
 Sparc: