[llvm] [RISC-V] Lower priority of X5(LR) during regalloc (PR #115867)

[Mark Goncharov via llvm-commits]

https://github.com/mga-sc created https://github.com/llvm/llvm-project/pull/115867

This patch allows not to use the x5 register if it can be replaced with another tmp register (x6-x7, x28-x31). Thus, we use link register less often, allowing the MachineOutliner pass to perform outline more often.

>From 0cfe485b2f85adde81a0f1f2f5049b6d8fb0928f Mon Sep 17 00:00:00 2001
From: Goncharov Mark <mark.goncharov at syntacore.com>
Date: Tue, 12 Nov 2024 13:18:49 +0000
Subject: [PATCH] [RISC-V] Lower priority of X5(LR) during regalloc

This patch allows not to use the x5 register if it
can be replaced with another tmp register (x6-x7, x28-x31).
Thus, we use link register less often, allowing the
MachineOutliner pass to perform outline more often.
---
 llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp    | 18 ++++++++++++++++++
 .../rvv/fixed-vectors-int-explodevector.ll     |  8 ++++----
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index ff250b2c9df819..ed9d61cdb852b0 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -23,6 +23,8 @@
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/Support/ErrorHandling.h"
+#include <algorithm>
+#include <unordered_set>
 
 #define GET_REGINFO_TARGET_DESC
 #include "RISCVGenRegisterInfo.inc"
@@ -929,5 +931,21 @@ bool RISCVRegisterInfo::getRegAllocationHints(
     if (TwoAddrHints.count(OrderReg))
       Hints.push_back(OrderReg);
 
+  // X5 register can be used by Machine Outliner to make a call to
+  // outlined function, while preserving the original return address
+  // in X1. Unless there's no other way, do not use X5 register for
+  // computation if other tmp registers are available.
+  if (auto X5It = std::find(Hints.begin(), Hints.end(), RISCV::X5);
+      X5It != Hints.end()) {
+    std::unordered_set<MCPhysReg> TmpRegs = {
+        RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31};
+    auto CheckTmpReg = [&TmpRegs](const MCPhysReg &PR) {
+      return TmpRegs.find(PR) != TmpRegs.end();
+    };
+    auto AnotherTmpIt = std::find_if(Hints.begin(), Hints.end(), CheckTmpReg);
+    if (AnotherTmpIt != Hints.end())
+      Hints.erase(X5It);
+  }
+
   return BaseImplRetVal;
 }
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
index 6cab1bc2185287..cbf258de9c2ad5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
@@ -1060,10 +1060,10 @@ define i64 @explode_16xi64(<16 x i64> %v) {
 ; RV64-NEXT:    add a5, a5, a6
 ; RV64-NEXT:    add a5, a5, a7
 ; RV64-NEXT:    add a0, a0, a5
-; RV64-NEXT:    add t0, t0, t1
-; RV64-NEXT:    add t0, t0, t2
-; RV64-NEXT:    add t0, t0, t3
-; RV64-NEXT:    add a0, a0, t0
+; RV64-NEXT:    add t1, t0, t1
+; RV64-NEXT:    add t1, t1, t2
+; RV64-NEXT:    add t1, t1, t3
+; RV64-NEXT:    add a0, a0, t1
 ; RV64-NEXT:    add t4, t4, t5
 ; RV64-NEXT:    add a0, a0, t4
 ; RV64-NEXT:    addi sp, s0, -256