[llvm] [AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (PR #113634)
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 12 05:14:54 PST 2024
================
@@ -167,45 +184,60 @@ multiclass VInterpF16Pat <SDPatternOperator op, Instruction inst,
def : VInterpF32Pat<int_amdgcn_interp_inreg_p10, V_INTERP_P10_F32_inreg>;
def : VInterpF32Pat<int_amdgcn_interp_inreg_p2, V_INTERP_P2_F32_inreg>;
+
+let True16Predicate = UseFakeTrue16Insts in {
defm : VInterpF16Pat<int_amdgcn_interp_inreg_p10_f16,
- V_INTERP_P10_F16_F32_inreg, f32,
+ V_INTERP_P10_F16_F32_inreg_fake16, f32,
[VINTERPModsHi, VINTERPMods, VINTERPModsHi]>;
defm : VInterpF16Pat<int_amdgcn_interp_inreg_p2_f16,
- V_INTERP_P2_F16_F32_inreg, f16,
+ V_INTERP_P2_F16_F32_inreg_fake16, f16,
[VINTERPModsHi, VINTERPMods, VINTERPMods]>;
defm : VInterpF16Pat<int_amdgcn_interp_p10_rtz_f16,
- V_INTERP_P10_RTZ_F16_F32_inreg, f32,
+ V_INTERP_P10_RTZ_F16_F32_inreg_fake16, f32,
[VINTERPModsHi, VINTERPMods, VINTERPModsHi]>;
defm : VInterpF16Pat<int_amdgcn_interp_p2_rtz_f16,
- V_INTERP_P2_RTZ_F16_F32_inreg, f16,
+ V_INTERP_P2_RTZ_F16_F32_inreg_fake16, f16,
[VINTERPModsHi, VINTERPMods, VINTERPMods]>;
+}
//===----------------------------------------------------------------------===//
// VINTERP Real Instructions
//===----------------------------------------------------------------------===//
-multiclass VINTERP_Real_gfx11 <bits<7> op> {
- let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
- def _gfx11 :
- VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX11>,
- VINTERPe_gfx11<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
+multiclass VINTERP_Real_gfx11 <bits<7> op, string asmName> {
+ defvar ps = !cast<VOP3_Pseudo>(NAME);
+ let AssemblerPredicate = isGFX11Only,
+ DecoderNamespace = "GFX11" #
+ !if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {
+ def _gfx11 :
----------------
kosarev wrote:
Nit: indentation is off. +Same below.
https://github.com/llvm/llvm-project/pull/113634
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