[llvm] [RISCV] Override default sched policy (PR #115445)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> Non blocking, can you check that #107532 still spills? I have a feeling we still need to set microOpBufferSize otherwise latency always overrides register pressure

Yeah, it still spills. I think we can add generic models as what I commented before. :-)

https://github.com/llvm/llvm-project/pull/115445