[llvm] [llvm] Remove redundant control flow statements (NFC) (PR #115831)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 12 01:17:41 PST 2024
https://github.com/kazutakahirata updated https://github.com/llvm/llvm-project/pull/115831
>From d2ffe6c47e9f80f06e22ec93bc21e0bc725e192a Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Mon, 11 Nov 2024 23:21:59 -0800
Subject: [PATCH 1/2] [llvm] Remove redundant control flow statements (NFC)
Identified with readability-redundant-control-flow.
---
llvm/include/llvm/CodeGen/MachineFunction.h | 1 -
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 1 -
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 1 -
llvm/lib/IR/AsmWriter.cpp | 1 -
llvm/lib/IR/BasicBlock.cpp | 2 --
llvm/lib/Object/WasmObjectFile.cpp | 1 -
llvm/lib/ObjectYAML/DWARFEmitter.cpp | 1 -
llvm/lib/Passes/StandardInstrumentations.cpp | 2 --
llvm/lib/Support/APFloat.cpp | 1 -
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 --
llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp | 1 -
llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp | 5 -----
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 2 --
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 --
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 1 -
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 1 -
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 1 -
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 1 -
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 --
llvm/lib/Transforms/Scalar/JumpThreading.cpp | 2 --
llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 1 -
llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp | 1 -
llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp | 1 -
23 files changed, 34 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 21b192a27cad9d..9c5d6555351d08 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -468,7 +468,6 @@ class LLVM_ABI MachineFunction {
/// Callback before changing MCInstrDesc. This should not modify the MI
/// directly.
virtual void MF_HandleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID) {
- return;
}
};
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 05a7e195e95ba7..675f55d8086bc3 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3551,7 +3551,6 @@ void IRTranslator::translateDbgValueRecord(Value *V, bool HasArgList,
// pretty baked in right now.
MIRBuilder.buildDirectDbgValue(Reg, Variable, Expression);
}
- return;
}
void IRTranslator::translateDbgDeclareRecord(Value *Address, bool HasArgList,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 3b046aa25f5444..35ad0b259fa55f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1223,7 +1223,6 @@ void SelectionDAGBuilder::handleDebugDeclare(Value *Address,
<< " (could not emit func-arg dbg_value)\n");
}
}
- return;
}
void SelectionDAGBuilder::visitDbgInfo(const Instruction &I) {
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index 8716a7ce2aec36..3c1cb76622bbb7 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -4679,7 +4679,6 @@ void AssemblyWriter::printDbgMarker(const DbgMarker &Marker) {
Out << " DbgMarker -> { ";
printInstruction(*Marker.MarkedInstr);
Out << " }";
- return;
}
void AssemblyWriter::printDbgRecord(const DbgRecord &DR) {
diff --git a/llvm/lib/IR/BasicBlock.cpp b/llvm/lib/IR/BasicBlock.cpp
index 39cefa5280c62f..0efc04cb2c8679 100644
--- a/llvm/lib/IR/BasicBlock.cpp
+++ b/llvm/lib/IR/BasicBlock.cpp
@@ -798,8 +798,6 @@ void BasicBlock::spliceDebugInfoEmptyBlock(BasicBlock::iterator Dest,
return;
createMarker(Dest)->absorbDebugValues(*First->DebugMarker, InsertAtHead);
-
- return;
}
void BasicBlock::spliceDebugInfo(BasicBlock::iterator Dest, BasicBlock *Src,
diff --git a/llvm/lib/Object/WasmObjectFile.cpp b/llvm/lib/Object/WasmObjectFile.cpp
index 35f152d5ece8ba..ef19c3c62835f8 100644
--- a/llvm/lib/Object/WasmObjectFile.cpp
+++ b/llvm/lib/Object/WasmObjectFile.cpp
@@ -1242,7 +1242,6 @@ Error WasmObjectFile::parseTypeSection(ReadContext &Ctx) {
while (ParamCount--) {
uint32_t ParamType = readUint8(Ctx);
Sig.Params.push_back(parseValType(Ctx, ParamType));
- continue;
}
uint32_t ReturnCount = readVaruint32(Ctx);
while (ReturnCount--) {
diff --git a/llvm/lib/ObjectYAML/DWARFEmitter.cpp b/llvm/lib/ObjectYAML/DWARFEmitter.cpp
index 15100f3f569fab..83776c9850d80f 100644
--- a/llvm/lib/ObjectYAML/DWARFEmitter.cpp
+++ b/llvm/lib/ObjectYAML/DWARFEmitter.cpp
@@ -745,7 +745,6 @@ void emitDebugNamesHeader(raw_ostream &OS, bool IsLittleEndian,
writeInteger(AbbrevSize, OS, IsLittleEndian);
writeInteger(uint32_t(AugmentationString.size()), OS, IsLittleEndian);
OS.write(AugmentationString.data(), AugmentationString.size());
- return;
}
/// Emits the abbreviations for a DebugNames section.
diff --git a/llvm/lib/Passes/StandardInstrumentations.cpp b/llvm/lib/Passes/StandardInstrumentations.cpp
index 5a3bf8884cd542..6259f8f736c80b 100644
--- a/llvm/lib/Passes/StandardInstrumentations.cpp
+++ b/llvm/lib/Passes/StandardInstrumentations.cpp
@@ -2547,7 +2547,6 @@ void DroppedVariableStats::runBeforePass(StringRef PassID, Any IR) {
return this->runOnModule(M, true);
if (auto *F = unwrapIR<Function>(IR))
return this->runOnFunction(F, true);
- return;
}
void DroppedVariableStats::runOnFunction(const Function *F, bool Before) {
@@ -2661,7 +2660,6 @@ void DroppedVariableStats::runAfterPass(StringRef PassID, Any IR,
DebugVariablesStack.pop_back();
InlinedAts.pop_back();
- return;
}
bool DroppedVariableStats::isScopeChildOfOrEqualTo(DIScope *Scope,
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 5cb6de9bd847e6..c566d489d11b03 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -3947,7 +3947,6 @@ void IEEEFloat::initFromFloat8E8M0FNUAPInt(const APInt &api) {
// Handle fcNormal...
category = fcNormal;
exponent = myexponent - 127; // 127 is bias
- return;
}
template <const fltSemantics &S>
void IEEEFloat::initFromIEEEAPInt(const APInt &api) {
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 97050ba2476ff5..1969c830f4d312 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1533,7 +1533,6 @@ void AArch64DAGToDAGISel::SelectPtrauthAuth(SDNode *N) {
SDNode *AUT = CurDAG->getMachineNode(AArch64::AUT, DL, MVT::i64, Ops);
ReplaceNode(N, AUT);
- return;
}
void AArch64DAGToDAGISel::SelectPtrauthResign(SDNode *N) {
@@ -1567,7 +1566,6 @@ void AArch64DAGToDAGISel::SelectPtrauthResign(SDNode *N) {
SDNode *AUTPAC = CurDAG->getMachineNode(AArch64::AUTPAC, DL, MVT::i64, Ops);
ReplaceNode(N, AUTPAC);
- return;
}
bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
index a6a8597f22a4a2..067fc981740331 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
@@ -178,7 +178,6 @@ static void instrumentAddressImpl(Module &M, IRBuilder<> &IRB,
generateCrashCode(M, IRB, IntptrTy, CrashTerm, AddrLong, IsWrite,
AccessSizeIndex, SizeArgument, Recover);
Crash->setDebugLoc(OrigIns->getDebugLoc());
- return;
}
void instrumentAddress(Module &M, IRBuilder<> &IRB, Instruction *OrigIns,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
index dfa91904a734d0..488dc393232369 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
@@ -358,7 +358,6 @@ void AMDGPUSwLowerLDS::buildSwLDSGlobal(Function *Func) {
GlobalValue::SanitizerMetadata MD;
MD.NoAddress = true;
LDSParams.SwLDS->setSanitizerMetadata(MD);
- return;
}
void AMDGPUSwLowerLDS::buildSwDynLDSGlobal(Function *Func) {
@@ -377,7 +376,6 @@ void AMDGPUSwLowerLDS::buildSwDynLDSGlobal(Function *Func) {
GlobalValue::SanitizerMetadata MD;
MD.NoAddress = true;
LDSParams.SwDynLDS->setSanitizerMetadata(MD);
- return;
}
void AMDGPUSwLowerLDS::populateSwLDSAttributeAndMetadata(Function *Func) {
@@ -496,7 +494,6 @@ void AMDGPUSwLowerLDS::populateSwMetadataGlobal(Function *Func) {
GlobalValue::SanitizerMetadata MD;
MD.NoAddress = true;
LDSParams.SwLDSMetadata->setSanitizerMetadata(MD);
- return;
}
void AMDGPUSwLowerLDS::populateLDSToReplacementIndicesMap(Function *Func) {
@@ -522,7 +519,6 @@ void AMDGPUSwLowerLDS::populateLDSToReplacementIndicesMap(Function *Func) {
PopulateIndices(LDSParams.IndirectAccess.StaticLDSGlobals, Idx);
PopulateIndices(LDSParams.DirectAccess.DynamicLDSGlobals, Idx);
PopulateIndices(LDSParams.IndirectAccess.DynamicLDSGlobals, Idx);
- return;
}
static void replacesUsesOfGlobalInFunction(Function *Func, GlobalVariable *GV,
@@ -1118,7 +1114,6 @@ void AMDGPUSwLowerLDS::initAsanInfo() {
false, &Offset, &Scale, &OrShadowOffset);
AsanInfo.Scale = Scale;
AsanInfo.Offset = Offset;
- return;
}
bool AMDGPUSwLowerLDS::run() {
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 88caf8196b3c90..93e8527de5628d 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -244,8 +244,6 @@ void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) {
O << "SCOPE_SYS";
else
llvm_unreachable("unexpected scope policy value");
-
- return;
}
void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 37dc433d154f64..cef7d78feac315 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -14012,8 +14012,6 @@ static void placeSources(ByteProvider<SDValue> &Src0,
{*Src1.Src,
((Src1.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)),
Src1.SrcOffset / 4});
-
- return;
}
static SDValue resolveSources(SelectionDAG &DAG, SDLoc SL,
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index febbc95ec0db4c..b6ed035607d960 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -998,7 +998,6 @@ void HexagonDAGToDAGISel::SelectFDiv(SDNode *N) {
FastFDiv(N);
else
FDiv(N);
- return;
}
void HexagonDAGToDAGISel::Select(SDNode *N) {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 3c331cee8f7648..07661a50450113 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -5456,7 +5456,6 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
BuildMI(*MBB, ++Iter, DL, TII->get(PPC::COPY), SrcReg)
.addReg(NewDefinedReg, RegState::Kill, PPC::sub_32);
LV->recomputeForSingleDefVirtReg(NewDefinedReg);
- return;
}
// The isSignOrZeroExtended function is recursive. The parameter BinOpDepth
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index b762cac8ea4f3a..412d6deb569b0a 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -500,7 +500,6 @@ bool PPCMIPeephole::simplifyCode() {
NumConvertedToImmediateForm++;
SomethingChanged = true;
Simplified = true;
- continue;
}
}
} while (SomethingChanged && FixedPointRegToImm);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 1a042375d0720e..3c95f01b86361c 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -578,7 +578,6 @@ static void getOperandsForBranch(Register CondReg, RISCVCC::CondCode &CC,
}
CC = getRISCVCCFromICmp(Pred);
- return;
}
bool RISCVInstructionSelector::select(MachineInstr &MI) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 79c0437e9e9e9c..3df8eca8cae7fb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9390,8 +9390,6 @@ static inline void promoteVCIXScalar(const SDValue &Op,
isa<ConstantSDNode>(ScalarOp) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND;
ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp);
}
-
- return;
}
static void processVCIXOperands(SDValue &OrigOp,
diff --git a/llvm/lib/Transforms/Scalar/JumpThreading.cpp b/llvm/lib/Transforms/Scalar/JumpThreading.cpp
index 7bc550c51a73d6..16110cd25bc61c 100644
--- a/llvm/lib/Transforms/Scalar/JumpThreading.cpp
+++ b/llvm/lib/Transforms/Scalar/JumpThreading.cpp
@@ -2109,8 +2109,6 @@ void JumpThreadingPass::cloneInstructions(ValueToValueMapTy &ValueMapping,
for (DbgVariableRecord &DVR : filterDbgVars(DVRRange))
RetargetDbgVariableRecordIfPossible(&DVR);
}
-
- return;
}
/// Attempt to thread through two successive basic blocks.
diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
index 7bffd4da75a5bf..1454305970ce3a 100644
--- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
@@ -425,7 +425,6 @@ DbgVariableRecordsRemoveRedundantDbgInstrsUsingBackwardScan(BasicBlock *BB) {
}
ToBeRemoved.push_back(&DVR);
- continue;
}
// Sequence with consecutive dbg.value instrs ended. Clear the map to
// restart identifying redundant instructions if case we find another
diff --git a/llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp b/llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
index 7421763dd7a427..0175deb1c848dc 100644
--- a/llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
+++ b/llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
@@ -1213,7 +1213,6 @@ void SourceCoverageViewHTML::renderMCDCView(raw_ostream &OS, MCDCView &MRV,
OS << EndPre;
OS << EndExpansionDiv;
}
- return;
}
void SourceCoverageViewHTML::renderInstantiationView(raw_ostream &OS,
diff --git a/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp b/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
index 364b80c36bac8d..cb423ce142fb7d 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
@@ -308,7 +308,6 @@ bool PatternParser::parseInstructionPatternMIFlags(InstructionPattern &IP,
return false;
FI.addUnsetFlag(R);
- continue;
}
continue;
>From cebf88f028b73b06f68462cd9dc56010127b8986 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Tue, 12 Nov 2024 01:17:27 -0800
Subject: [PATCH 2/2] Trigger build
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