[llvm] 375bb38 - [RISCV][GISel] Add i32 zext.h pattern for Zbkb.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-11-11T15:29:28-08:00
New Revision: 375bb38f728874c371ea044bcd62b3869ea25e98

URL: https://github.com/llvm/llvm-project/commit/375bb38f728874c371ea044bcd62b3869ea25e98
DIFF: https://github.com/llvm/llvm-project/commit/375bb38f728874c371ea044bcd62b3869ea25e98.diff

LOG: [RISCV][GISel] Add i32 zext.h pattern for Zbkb.

This resolves a FIXME and reduces tests diffs from later patches
remove i32 as a legal type.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVGISel.td
    llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
    llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 75b486ce697e2b..dc8e0ced7f1e80 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -249,6 +249,10 @@ def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
 def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
+let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in {
+def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (PACKW GPR:$rs, (XLenVT X0))>;
+} // Predicates = [HasStdExtZbb, IsRV64]
+
 let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
 def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i32 (or  GPR:$rs1, (not GPR:$rs2))), (ORN  GPR:$rs1, GPR:$rs2)>;

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
index a6d3ddbf199931..302814f4c86e94 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
@@ -471,19 +471,11 @@ define i16 @srli_i16(i16 %a) nounwind {
 ; RV64I-NEXT:    srliw a0, a0, 6
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBB-LABEL: srli_i16:
-; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    zext.h a0, a0
-; RV64ZBB-NEXT:    srliw a0, a0, 6
-; RV64ZBB-NEXT:    ret
-;
-; RV64ZBKB-LABEL: srli_i16:
-; RV64ZBKB:       # %bb.0:
-; RV64ZBKB-NEXT:    lui a1, 16
-; RV64ZBKB-NEXT:    addi a1, a1, -1
-; RV64ZBKB-NEXT:    and a0, a0, a1
-; RV64ZBKB-NEXT:    srliw a0, a0, 6
-; RV64ZBKB-NEXT:    ret
+; RV64ZBB-ZBKB-LABEL: srli_i16:
+; RV64ZBB-ZBKB:       # %bb.0:
+; RV64ZBB-ZBKB-NEXT:    zext.h a0, a0
+; RV64ZBB-ZBKB-NEXT:    srliw a0, a0, 6
+; RV64ZBB-ZBKB-NEXT:    ret
   %1 = lshr i16 %a, 6
   ret i16 %1
 }

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
index b449b7d1beaaec..a8c937db552bc2 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
@@ -18,12 +18,9 @@ define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
 ;
 ; RV64ZBKB-LABEL: pack_i32:
 ; RV64ZBKB:       # %bb.0:
-; RV64ZBKB-NEXT:    lui a2, 16
-; RV64ZBKB-NEXT:    addi a2, a2, -1
-; RV64ZBKB-NEXT:    and a0, a0, a2
-; RV64ZBKB-NEXT:    slli a1, a1, 16
+; RV64ZBKB-NEXT:    zext.h a0, a0
+; RV64ZBKB-NEXT:    slliw a1, a1, 16
 ; RV64ZBKB-NEXT:    or a0, a1, a0
-; RV64ZBKB-NEXT:    sext.w a0, a0
 ; RV64ZBKB-NEXT:    ret
   %shl = and i32 %a, 65535
   %shl1 = shl i32 %b, 16
@@ -368,9 +365,7 @@ define signext i32 @pack_i32_allWUsers(i16 zeroext %0, i16 zeroext %1, i16 zeroe
 ; RV64ZBKB-LABEL: pack_i32_allWUsers:
 ; RV64ZBKB:       # %bb.0:
 ; RV64ZBKB-NEXT:    add a0, a1, a0
-; RV64ZBKB-NEXT:    lui a1, 16
-; RV64ZBKB-NEXT:    addi a1, a1, -1
-; RV64ZBKB-NEXT:    and a0, a0, a1
+; RV64ZBKB-NEXT:    zext.h a0, a0
 ; RV64ZBKB-NEXT:    slli a0, a0, 16
 ; RV64ZBKB-NEXT:    or a0, a0, a2
 ; RV64ZBKB-NEXT:    sext.w a0, a0
@@ -404,7 +399,6 @@ define i64 @pack_i64_imm() {
   ret i64 1157442765409226768 ; 0x0101010101010101
 }
 
-; FIXME: Use zext.h
 define i32 @zexth_i32(i32 %a) nounwind {
 ; RV64I-LABEL: zexth_i32:
 ; RV64I:       # %bb.0:
@@ -415,9 +409,7 @@ define i32 @zexth_i32(i32 %a) nounwind {
 ;
 ; RV64ZBKB-LABEL: zexth_i32:
 ; RV64ZBKB:       # %bb.0:
-; RV64ZBKB-NEXT:    lui a1, 16
-; RV64ZBKB-NEXT:    addiw a1, a1, -1
-; RV64ZBKB-NEXT:    and a0, a0, a1
+; RV64ZBKB-NEXT:    zext.h a0, a0
 ; RV64ZBKB-NEXT:    ret
   %and = and i32 %a, 65535
   ret i32 %and