[llvm] 615e28e - [RISCV][GISel] Remove s32 as a legal type for G_SMUL on RV64.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 11 15:09:07 PST 2024
Author: Craig Topper
Date: 2024-11-11T15:08:50-08:00
New Revision: 615e28e6271025cc3dbdf8c04e9902a5dd8b2b0c
URL: https://github.com/llvm/llvm-project/commit/615e28e6271025cc3dbdf8c04e9902a5dd8b2b0c
DIFF: https://github.com/llvm/llvm-project/commit/615e28e6271025cc3dbdf8c04e9902a5dd8b2b0c.diff
LOG: [RISCV][GISel] Remove s32 as a legal type for G_SMUL on RV64.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/lib/Target/RISCV/RISCVGISel.td
llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 2643a1a708dd25..581314f7efab17 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -414,9 +414,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
if (ST.hasStdExtZmmul()) {
getActionDefinitionsBuilder(G_MUL)
- .legalFor({s32, sXLen})
+ .legalFor({sXLen})
.widenScalarToNextPow2(0)
- .clampScalar(0, s32, sXLen);
+ .clampScalar(0, sXLen, sXLen);
// clang-format off
getActionDefinitionsBuilder({G_SMULH, G_UMULH})
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 83018f28176564..75b486ce697e2b 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -238,14 +238,6 @@ def : Pat<(shl (zext GPR:$rs), uimm5:$shamt),
(SRLI (i64 (SLLI GPR:$rs, 32)), (ImmSubFrom32 uimm5:$shamt))>;
}
-//===----------------------------------------------------------------------===//
-// M RV64 i32 legalization patterns.
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasStdExtZmmul, IsRV64] in {
-def : PatGprGpr<mul, MULW, i32, i32>;
-}
-
//===----------------------------------------------------------------------===//
// Zb* RV64 i32 patterns not used by SelectionDAG.
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
index 14ff9e01ab3bc2..4f0d904cad375c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
@@ -333,7 +333,7 @@ define i32 @mul_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: mul_i32:
; RV64IM: # %bb.0: # %entry
-; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = mul i32 %a, %b
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
index fad9effdd4030b..b203e9ed88a717 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
@@ -3,30 +3,20 @@
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
define i32 @freeze_int(i32 %x) {
-; RV32-LABEL: freeze_int:
-; RV32: # %bb.0:
-; RV32-NEXT: mul a0, a0, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: freeze_int:
-; RV64: # %bb.0:
-; RV64-NEXT: mulw a0, a0, a0
-; RV64-NEXT: ret
+; CHECK-LABEL: freeze_int:
+; CHECK: # %bb.0:
+; CHECK-NEXT: mul a0, a0, a0
+; CHECK-NEXT: ret
%y1 = freeze i32 %x
%t1 = mul i32 %y1, %y1
ret i32 %t1
}
define i5 @freeze_int2(i5 %x) {
-; RV32-LABEL: freeze_int2:
-; RV32: # %bb.0:
-; RV32-NEXT: mul a0, a0, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: freeze_int2:
-; RV64: # %bb.0:
-; RV64-NEXT: mulw a0, a0, a0
-; RV64-NEXT: ret
+; CHECK-LABEL: freeze_int2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: mul a0, a0, a0
+; CHECK-NEXT: ret
%y1 = freeze i5 %x
%t1 = mul i5 %y1, %y1
ret i5 %t1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
index 605830ff4f971b..18b2fcaa45014e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
@@ -2,33 +2,6 @@
# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
----
-name: mul_i32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x10, $x11
-
- ; RV64I-LABEL: name: mul_i32
- ; RV64I: liveins: $x10, $x11
- ; RV64I-NEXT: {{ $}}
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
- ; RV64I-NEXT: [[MULW:%[0-9]+]]:gpr = MULW [[COPY]], [[COPY1]]
- ; RV64I-NEXT: $x10 = COPY [[MULW]]
- ; RV64I-NEXT: PseudoRET implicit $x10
- %0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s64) = COPY $x11
- %3:gprb(s32) = G_TRUNC %2(s64)
- %4:gprb(s32) = G_MUL %1, %3
- %5:gprb(s64) = G_ANYEXT %4(s32)
- $x10 = COPY %5(s64)
- PseudoRET implicit $x10
-
-...
---
name: sdiv_i32
legalized: true
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
index f4ea4f5eb43aa3..3255a73b7916c9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
@@ -45,12 +45,16 @@ body: |
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND8]], [[C]]
- ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND8]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
+ ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C7]](s32)
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[LSHR6]]
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctlz_i8
@@ -120,13 +124,16 @@ body: |
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]]
- ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND9]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C4]](s32)
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[LSHR7]]
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctlz_i16
@@ -192,12 +199,15 @@ body: |
; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C8]]
- ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND3]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C9]](s32)
; RV64I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR8]]
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctlz_i32
@@ -319,12 +329,16 @@ body: |
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND8]], [[C]]
- ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND8]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
+ ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C7]](s32)
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[LSHR6]]
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctlz_zero_undef_i8
@@ -394,13 +408,16 @@ body: |
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]]
- ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND9]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C4]](s32)
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[LSHR7]]
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctlz_zero_undef_i16
@@ -466,12 +483,15 @@ body: |
; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C8]]
- ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND3]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C9]](s32)
; RV64I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR8]]
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctlz_zero_undef_i32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
index 48595dc9809c74..d55528aa4b95f4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
@@ -36,10 +36,14 @@ body: |
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND5]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctpop_i8
@@ -93,11 +97,14 @@ body: |
; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C7]]
- ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND5]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C8]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctpop_i16
@@ -147,10 +154,13 @@ body: |
; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND3]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C7]](s32)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: ctpop_i32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
index c3b6d357d241d7..500296291c729f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
@@ -39,10 +39,14 @@ body: |
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C1]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND6]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C2]]
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C8]](s32)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: cttz_i8
@@ -100,11 +104,14 @@ body: |
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C8]]
- ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C2]]
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND6]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C2]]
; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C9]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: cttz_i16
@@ -159,10 +166,13 @@ body: |
; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C6]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C7]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND4]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C8]](s32)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: cttz_i32
@@ -265,10 +275,14 @@ body: |
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C1]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND6]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C2]]
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C8]](s32)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: cttz_zero_undef_i8
@@ -326,11 +340,14 @@ body: |
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C8]]
- ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C2]]
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND6]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C2]]
; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C9]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: cttz_zero_undef_i16
@@ -385,10 +402,13 @@ body: |
; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C6]]
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C7]]
- ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32)
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND4]](s32)
+ ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32)
+ ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
+ ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
+ ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C8]](s32)
+ ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: cttz_zero_undef_i32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir
index 39d9c5b7dfd1e2..a7d17feb0d1010 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir
@@ -10,11 +10,8 @@ body: |
; CHECK-LABEL: name: mul_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
- ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
@@ -33,11 +30,8 @@ body: |
; CHECK-LABEL: name: mul_i15
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
- ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
@@ -56,11 +50,8 @@ body: |
; CHECK-LABEL: name: mul_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
- ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
@@ -79,11 +70,8 @@ body: |
; CHECK-LABEL: name: mul_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
- ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
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