[llvm] [AMDGPU] Add intrinsic readanylane (PR #115696)

[Jay Foad via llvm-commits]

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@@ -546,6 +546,10 @@ def SI_MASKED_UNREACHABLE : SPseudoInstSI <(outs), (ins),
   let maybeAtomic = 0;
 }
 
+def SI_READANYLANE : SPseudoInstSI <(outs SReg_32:$dst), (ins VGPR_32:$src)> {
+  let SALU = 1;
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jayfoad wrote:

Should be a VALU instruction like readfirstlane is. Maybe define it with `VPseudoInstSI`?

https://github.com/llvm/llvm-project/pull/115696