[llvm] [AArch64][PAC] Move emission of LR checks in tail calls to AsmPrinter (PR #110705)

[Daniil Kovalev via llvm-commits]

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@@ -0,0 +1,59 @@
+; RUN: llc -mtriple aarch64-linux-pauthtest -o - %s \
+; RUN:     -aarch64-authenticated-lr-check-method=xpac-hint \
+; RUN:     -stop-before=aarch64-ptrauth \
+; RUN:     | FileCheck --check-prefix=MIR %s
+
+; RUN: llc -mtriple aarch64-linux-pauthtest -o - %s \
+; RUN:     -aarch64-authenticated-lr-check-method=xpac-hint \
+; RUN:     | FileCheck --check-prefix=ASM %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+
+; Test that expansion of AUTH_TCRETURN does not crash due to unavailability of
+; neither x16 nor x17 as a scratch register.
+define i32 @test_scratch_reg_nobti(ptr %callee, ptr %addr) #0 {
+entry:
+  ; Force spilling of LR
+  tail call void asm sideeffect "", "~{lr}"()
+  ; Clobber x0-x15 and x18-x29
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kovdan01 wrote:

Thanks for updating comments and tests!

> I guess we observe the case "... then it should use r18 as an additional temporary register", so it is probably handled the same way as x9-x15.

Yes, it's probably this case. But, even though x18 is handled as a temporary register in this case, it does not look correct to have `mov x17, x0; mov x18, x1; /* clobber x17 and x18 */; braa x18, x17`, doesn't it? I also might be missing smth and would be glad if you explain that. To achieve such assembly output, just add x16 and x17 to clobber list of the last `tail call void asm sideeffect` instruction.

https://github.com/llvm/llvm-project/pull/110705