[llvm] [AMDGPU] Add intrinsic readanylane (PR #115696)

[Xin Russell Liu via llvm-commits]

GinShio wrote:

> Transforming A-->B is not safe for `readfirstlane`, but it is safe for `readanylane` (because if x is uniform outside the `if` then it must also be uniform inside the `if`). Transforming B-->A is not safe for `readfirstlane` and not safe for `readanylane`.

Sorry, I don't quite understand why the latter is unsafe. (B-->A for `readanylane`)
In my understand, if x is uniform, `readanylane` is not affected by exec flag.

```mermaid
block-beta
  columns 8
  IfTh0[" "] IfTh1["42"] IfTh2["42"] IfTh3["42"] IfTh4["42"] IfTh5[" "] IfTh6["42"] IfTh7["42"]
  ThenTh0[" "] ThenTh1["42"] ThenTh2["42"] ThenTh3["42"] ThenTh4["42"] ThenTh5[" "] ThenTh6["42"] ThenTh7["42"]
  ElseTh0[" "] ElseTh1["42"] ElseTh2["42"] ElseTh3["42"] ElseTh4["42"] ElseTh5[" "] ElseTh6["42"] ElseTh7["42"]

  classDef disable fill:#808080,stroke:#333;
  classDef convergence fill:#218733,stroke:#333;
  classDef then fill:#A93376,stroke:#333;
  classDef else fill:#65CBEE,stroke:#333;
  class IfTh0,IfTh5,IfTh7 disable
  class IfTh1,IfTh2,IfTh3,IfTh4,IfTh6,IfTh7 convergence
  class ThenTh0,ThenTh1,ThenTh2,ThenTh4,ThenTh5 disable
  class ThenTh3,ThenTh6,ThenTh7 then
  class ElseTh0,ElseTh3,ElseTh5,ElseTh6,ElseTh7 disable
  class ElseTh1,ElseTh2,ElseTh4 else
```

For example, the 1st line is *if-block*, then it is *then-block*, and the last *else-block*.
Looks like reading data is a safe behavior no matter which bb it is in.

Could you help me point out my mistake?

https://github.com/llvm/llvm-project/pull/115696