[llvm] a5d09f4 - [GlobalISel] Add G_STEP_VECTOR instruction (#115598)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 11 01:45:06 PST 2024
Author: Thorsten Schütt
Date: 2024-11-11T10:45:02+01:00
New Revision: a5d09f4ad94fab718e787fb6dce7933e7742eb1b
URL: https://github.com/llvm/llvm-project/commit/a5d09f4ad94fab718e787fb6dce7933e7742eb1b
DIFF: https://github.com/llvm/llvm-project/commit/a5d09f4ad94fab718e787fb6dce7933e7742eb1b.diff
LOG: [GlobalISel] Add G_STEP_VECTOR instruction (#115598)
aka llvm.stepvector Intrinsic
Added:
llvm/test/MachineVerifier/test_step-vector.mir
Modified:
llvm/docs/GlobalISel/GenericOpcode.rst
llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/include/llvm/Support/TargetOpcodes.def
llvm/include/llvm/Target/GenericOpcodes.td
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Removed:
################################################################################
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 8920530dc3f1a1..076dc7fa93e565 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -753,6 +753,24 @@ The type of the operand must be equal to or larger than the vector element
type. If the operand is larger than the vector element type, the scalar is
implicitly truncated to the vector element type.
+G_STEP_VECTOR
+^^^^^^^^^^^^^
+
+Create a scalable vector where all lanes are linear sequences starting at 0
+with a given unsigned step.
+
+The type of the operand must be equal to the vector element type. Arithmetic
+is performed modulo the bitwidth of the element. The step must be > 0.
+Otherwise the vector is zero.
+
+.. code-block::
+
+ %0:_(<vscale x 2 x s64>) = G_STEP_VECTOR i64 4
+
+ %1:_(<vscale x s32>) = G_STEP_VECTOR i32 4
+
+ 0, 1*Step, 2*Step, 3*Step, 4*Step, ...
+
G_VECTOR_COMPRESS
^^^^^^^^^^^^^^^^^
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index cd7ebcf54c9e1e..4de14dee190fb3 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -906,6 +906,18 @@ class GVScale : public GenericMachineInstr {
};
};
+/// Represents a step vector.
+class GStepVector : public GenericMachineInstr {
+public:
+ uint64_t getStep() const {
+ return getOperand(1).getCImm()->getValue().getZExtValue();
+ }
+
+ static bool classof(const MachineInstr *MI) {
+ return MI->getOpcode() == TargetOpcode::G_STEP_VECTOR;
+ };
+};
+
/// Represents an integer subtraction.
class GSub : public GIntBinOp {
public:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index a38dd34a17097a..3516065f9b6cb3 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1172,6 +1172,17 @@ class MachineIRBuilder {
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
const SrcOp &Op, unsigned Index);
+ /// Build and insert \p Res = G_STEP_VECTOR \p Step
+ ///
+ /// G_STEP_VECTOR returns a scalable vector of linear sequence of step \p Step
+ /// into \p Res.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res must be a generic virtual register with scalable vector type.
+ ///
+ /// \return a MachineInstrBuilder for the newly created instruction.
+ MachineInstrBuilder buildStepVector(const DstOp &Res, unsigned Step);
+
/// Build and insert \p Res = G_VSCALE \p MinElts
///
/// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 0c4c6ccd5c568e..17987935ed3cf4 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -776,6 +776,9 @@ HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
/// Generic splatvector.
HANDLE_TARGET_OPCODE(G_SPLAT_VECTOR)
+/// Generic stepvector.
+HANDLE_TARGET_OPCODE(G_STEP_VECTOR)
+
/// Generic masked compress.
HANDLE_TARGET_OPCODE(G_VECTOR_COMPRESS)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 62bb9789afe5d2..60606db078b374 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1590,6 +1590,13 @@ def G_SPLAT_VECTOR: GenericInstruction {
let hasSideEffects = false;
}
+// Generic stepvector.
+def G_STEP_VECTOR: GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins unknown:$step);
+ let hasSideEffects = false;
+}
+
// Generic masked compress.
def G_VECTOR_COMPRESS: GenericInstruction {
let OutOperandList = (outs type0:$dst);
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 02dbe781babdba..c5e5c926160e2c 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -809,6 +809,17 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
}
+MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res,
+ unsigned Step) {
+ ConstantInt *CI =
+ ConstantInt::get(getMF().getFunction().getContext(), APInt(64, Step));
+ auto StepVector = buildInstr(TargetOpcode::G_STEP_VECTOR);
+ StepVector->setDebugLoc(DebugLoc());
+ Res.addDefToMIB(*getMRI(), StepVector);
+ StepVector.addCImm(CI);
+ return StepVector;
+}
+
MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
unsigned MinElts) {
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 10369928f7a05b..3910046a1652b1 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1731,6 +1731,36 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
}
break;
}
+ case TargetOpcode::G_STEP_VECTOR: {
+ if (!MI->getOperand(1).isCImm()) {
+ report("operand must be cimm", MI);
+ break;
+ }
+
+ if (!MI->getOperand(1).getCImm()->getValue().isStrictlyPositive()) {
+ report("step must be > 0", MI);
+ break;
+ }
+
+ LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+ if (!DstTy.isScalableVector()) {
+ report("Destination type must be a scalable vector", MI);
+ break;
+ }
+
+ // <vscale x 2 x p0>
+ if (!DstTy.getElementType().isScalar()) {
+ report("Destination element type must be scalar", MI);
+ break;
+ }
+
+ if (MI->getOperand(1).getCImm()->getBitWidth() !=
+ DstTy.getElementType().getScalarSizeInBits()) {
+ report("step bitwidth
diff ers from result type element bitwidth", MI);
+ break;
+ }
+ break;
+ }
case TargetOpcode::G_INSERT_SUBVECTOR: {
const MachineOperand &Src0Op = MI->getOperand(1);
if (!Src0Op.isReg()) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 6be99d0088f1cb..4fea713ee4c32c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -665,6 +665,9 @@
# DEBUG-NEXT: G_SPLAT_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_STEP_VECTOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_VECTOR_COMPRESS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index b611442eb9ba4e..3c078e9b7e2ddf 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -646,6 +646,9 @@
# DEBUG-NEXT: G_SPLAT_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_STEP_VECTOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_VECTOR_COMPRESS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
diff --git a/llvm/test/MachineVerifier/test_step-vector.mir b/llvm/test/MachineVerifier/test_step-vector.mir
new file mode 100644
index 00000000000000..b4a01bb258da10
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_step-vector.mir
@@ -0,0 +1,29 @@
+# RUN: not --crash llc -verify-machineinstrs -mtriple=arm64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name: g_step_vector
+body: |
+ bb.0:
+
+ %0:_(s32) = G_CONSTANT i32 4
+
+ ; CHECK: operand must be cimm
+ %1:_(s32) = G_STEP_VECTOR %0
+
+ ; CHECK: step must be > 0
+ %2:_(s32) = G_STEP_VECTOR i32 -1
+
+ ; CHECK: Destination type must be a scalable vector
+ %3:_(<4 x s64>) = G_STEP_VECTOR i32 5
+
+ ; CHECK: Destination element type must be scalar
+ %4:_(<vscale x 4 x p0>) = G_STEP_VECTOR i32 9
+
+ ; CHECK: step bitwidth
diff ers from result type element bitwidth
+ %6:_(<vscale x 2 x s33>) = G_STEP_VECTOR i32 56
+
+ %7:_(<vscale x 2 x s128>) = G_STEP_VECTOR i128 79
+
+...
+
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