[llvm] [AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (PR #115285)

[Pravin Jagtap via llvm-commits]

================
@@ -1808,6 +1808,8 @@ void SIRegisterInfo::buildSpillLoadStore(
                            .addReg(SubReg, getKillRegState(IsKill));
         if (NeedSuperRegDef)
           AccRead.addReg(ValueReg, RegState::ImplicitDefine);
+        if (NeedSuperRegImpOperand && (IsFirstSubReg || IsLastSubReg))
----------------
pravinjagtap wrote:

If we are keen on having the same behavior as `copyPhysReg`, how about submitting this patch first so that we will have same behavior in both the code paths (Spilling to VGPR + Spilling to Stack through VGPR) in this API? and then removing the conditional code which constraints the implicit for first and last spill instruction in the next patch? 

https://github.com/llvm/llvm-project/pull/115285