[llvm] [RISCV] Zabha/Zacas implies Zaamo (PR #115694)
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Mon Nov 11 00:29:17 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Jim Lin (tclin914)
<details>
<summary>Changes</summary>
The Zabha/Zacas extension depends upon the Zaamo extension.
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc.
---
Full diff: https://github.com/llvm/llvm-project/pull/115694.diff
5 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4-2)
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (-5)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4-4)
- (modified) llvm/test/MC/RISCV/attribute-arch.s (+1-1)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (-10)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index ad733e1488b5ca..6ec7f9ab78c0d4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -237,14 +237,16 @@ def HasStdExtAOrZaamo
def FeatureStdExtZabha
: RISCVExtension<"zabha", 1, 0,
- "'Zabha' (Byte and Halfword Atomic Memory Operations)">;
+ "'Zabha' (Byte and Halfword Atomic Memory Operations)",
+ [FeatureStdExtZaamo]>;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def FeatureStdExtZacas
: RISCVExtension<"zacas", 1, 0,
- "'Zacas' (Atomic Compare-And-Swap Instructions)">,
+ "'Zacas' (Atomic Compare-And-Swap Instructions)",
+ [FeatureStdExtZaamo]>,
RISCVExtensionBitmask<0, 26>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index de5b5c39c9ed27..c1bc441fc3f63d 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -760,11 +760,6 @@ Error RISCVISAInfo::checkDependency() {
if (XLen != 32 && Exts.count("zcf"))
return getError("'zcf' is only supported for 'rv32'");
- if (!(Exts.count("a") || Exts.count("zaamo")))
- for (auto Ext : {"zacas", "zabha"})
- if (Exts.count(Ext))
- return getExtensionRequiresError(Ext, "a' or 'zaamo");
-
if (Exts.count("xwchc") != 0) {
if (XLen != 32)
return getError("'xwchc' is only supported for 'rv32'");
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 7624071f4f93ec..f61b403cc7c539 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -428,11 +428,11 @@
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
-; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
+; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0"
; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1"
; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp1p0_zicsr2p0"
-; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zabha1p0"
+; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zaamo1p0_zabha1p0"
; RV32ZVBC32E: .attribute 5, "rv32i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0"
; RV32ZVKGS: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvkgs0p7_zvl32b1p0"
; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm1p0"
@@ -574,10 +574,10 @@
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
-; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
+; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zacas1p0"
; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp1p0_zicsr2p0"
-; RV64ZABHA: .attribute 5, "rv64i2p1_a2p1_zabha1p0"
+; RV64ZABHA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zabha1p0"
; RV64ZVBC32E: .attribute 5, "rv64i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0"
; RV64ZVKGS: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvkgs0p7_zvl32b1p0"
; RV64SSNPM: .attribute 5, "rv64i2p1_ssnpm1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 72a1db865e025d..30cf037b1f70a4 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -394,7 +394,7 @@
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
.attribute arch, "rv32ia_zacas1p0"
-# CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0"
+# CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0"
.attribute arch, "rv32izalasr0p1"
# CHECK: attribute 5, "rv32i2p1_zalasr0p1"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 09c0f4159cc7ee..08944659d78f46 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -660,16 +660,6 @@ TEST(ParseArchString, MissingDepency) {
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
"");
}
-
- for (StringRef Input : {"rv32i_zacas1p0"}) {
- EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
- "'zacas' requires 'a' or 'zaamo' extension to also be specified");
- }
-
- for (StringRef Input : {"rv32i_zabha"}) {
- EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
- "'zabha' requires 'a' or 'zaamo' extension to also be specified");
- }
}
TEST(ParseArchString, RejectsUnrecognizedProfileNames) {
``````````
</details>
https://github.com/llvm/llvm-project/pull/115694
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