[llvm] [DAGCombine] Remove oneuse restrictions for RISCV in folding (shl (add_nsw x, c1)), c2) and folding (shl(sext(add x, c1)), c2) in some scenarios (PR #101294)

[via llvm-commits]

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@@ -59668,3 +59668,19 @@ Align X86TargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
     return Align(1ULL << ExperimentalPrefInnermostLoopAlignment);
   return TargetLowering::getPrefLoopAlignment();
 }
+
+bool X86TargetLowering::isDesirableToCommuteWithShift(
+    const SDNode *N, CombineLevel Level) const {
+  using namespace llvm::SDPatternMatch;
+  assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
+          N->getOpcode() == ISD::SRL) &&
+         "Expected shift op");
+
+  SDValue ShiftLHS = N->getOperand(0);
+  SDValue Add;
+  if (sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add))))) ||
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LiqinWeng wrote:

Some architectures, such as ARM, use this logic（sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add)） to directly return true, which doesn't seem appropriate, so I didn't change it.


https://github.com/llvm/llvm-project/pull/101294