[llvm] 6bad451 - [AArch64] Extend vector mull test coverage. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 3 14:19:00 PST 2024
Author: David Green
Date: 2024-11-03T22:18:55Z
New Revision: 6bad4514c938b3b48c0c719b8dd98b3906f2c290
URL: https://github.com/llvm/llvm-project/commit/6bad4514c938b3b48c0c719b8dd98b3906f2c290
DIFF: https://github.com/llvm/llvm-project/commit/6bad4514c938b3b48c0c719b8dd98b3906f2c290.diff
LOG: [AArch64] Extend vector mull test coverage. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/aarch64-smull.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/aarch64-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
index 11397703b4442e..3c4901ade972ec 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
@@ -2402,6 +2402,856 @@ define <2 x i32> @do_stuff(<2 x i64> %0, <2 x i64> %1) {
ret <2 x i32> %final
}
+define <2 x i64> @lsr(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-NEON-LABEL: lsr:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: ushr v0.2d, v0.2d, #32
+; CHECK-NEON-NEXT: ushr v1.2d, v1.2d, #32
+; CHECK-NEON-NEXT: fmov x10, d1
+; CHECK-NEON-NEXT: fmov x11, d0
+; CHECK-NEON-NEXT: mov x8, v1.d[1]
+; CHECK-NEON-NEXT: mov x9, v0.d[1]
+; CHECK-NEON-NEXT: umull x10, w11, w10
+; CHECK-NEON-NEXT: umull x8, w9, w8
+; CHECK-NEON-NEXT: fmov d0, x10
+; CHECK-NEON-NEXT: mov v0.d[1], x8
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: lsr:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ushr v0.2d, v0.2d, #32
+; CHECK-SVE-NEXT: ushr v1.2d, v1.2d, #32
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: mul z0.d, p0/m, z0.d, z1.d
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #32
+; CHECK-GI-NEXT: ushr v1.2d, v1.2d, #32
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v1.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+ %x = lshr <2 x i64> %a, <i64 32, i64 32>
+ %y = lshr <2 x i64> %b, <i64 32, i64 32>
+ %z = mul nsw <2 x i64> %x, %y
+ ret <2 x i64> %z
+}
+
+define <2 x i64> @lsr_const(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-NEON-LABEL: lsr_const:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: movi v1.2s, #31
+; CHECK-NEON-NEXT: shrn v0.2s, v0.2d, #32
+; CHECK-NEON-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: lsr_const:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: movi v1.2s, #31
+; CHECK-SVE-NEXT: shrn v0.2s, v0.2d, #32
+; CHECK-SVE-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: lsr_const:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI79_0
+; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #32
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI79_0]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v1.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+ %x = lshr <2 x i64> %a, <i64 32, i64 32>
+ %z = mul nsw <2 x i64> %x, <i64 31, i64 31>
+ ret <2 x i64> %z
+}
+
+define <2 x i64> @asr(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-NEON-LABEL: asr:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: sshr v0.2d, v0.2d, #32
+; CHECK-NEON-NEXT: sshr v1.2d, v1.2d, #32
+; CHECK-NEON-NEXT: fmov x10, d1
+; CHECK-NEON-NEXT: fmov x11, d0
+; CHECK-NEON-NEXT: mov x8, v1.d[1]
+; CHECK-NEON-NEXT: mov x9, v0.d[1]
+; CHECK-NEON-NEXT: smull x10, w11, w10
+; CHECK-NEON-NEXT: smull x8, w9, w8
+; CHECK-NEON-NEXT: fmov d0, x10
+; CHECK-NEON-NEXT: mov v0.d[1], x8
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: asr:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: sshr v0.2d, v0.2d, #32
+; CHECK-SVE-NEXT: sshr v1.2d, v1.2d, #32
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: mul z0.d, p0/m, z0.d, z1.d
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #32
+; CHECK-GI-NEXT: sshr v1.2d, v1.2d, #32
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v1.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+ %x = ashr <2 x i64> %a, <i64 32, i64 32>
+ %y = ashr <2 x i64> %b, <i64 32, i64 32>
+ %z = mul nsw <2 x i64> %x, %y
+ ret <2 x i64> %z
+}
+
+define <2 x i64> @asr_const(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-NEON-LABEL: asr_const:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: sshr v0.2d, v0.2d, #32
+; CHECK-NEON-NEXT: fmov x9, d0
+; CHECK-NEON-NEXT: mov x8, v0.d[1]
+; CHECK-NEON-NEXT: lsl x10, x9, #5
+; CHECK-NEON-NEXT: lsl x11, x8, #5
+; CHECK-NEON-NEXT: sub x9, x10, x9
+; CHECK-NEON-NEXT: fmov d0, x9
+; CHECK-NEON-NEXT: sub x8, x11, x8
+; CHECK-NEON-NEXT: mov v0.d[1], x8
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: asr_const:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: mov w8, #31 // =0x1f
+; CHECK-SVE-NEXT: sshr v0.2d, v0.2d, #32
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: dup v1.2d, x8
+; CHECK-SVE-NEXT: mul z0.d, p0/m, z0.d, z1.d
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: asr_const:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI81_0
+; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #32
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI81_0]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v1.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+ %x = ashr <2 x i64> %a, <i64 32, i64 32>
+ %z = mul nsw <2 x i64> %x, <i64 31, i64 31>
+ ret <2 x i64> %z
+}
+
+define <8 x i16> @smulladdl_v8i8_v8i16(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-NEON-LABEL: smulladdl_v8i8_v8i16:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: smull v0.8h, v0.8b, v1.8b
+; CHECK-NEON-NEXT: saddw v0.8h, v0.8h, v2.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: smulladdl_v8i8_v8i16:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: smull v0.8h, v0.8b, v1.8b
+; CHECK-SVE-NEXT: saddw v0.8h, v0.8h, v2.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: smulladdl_v8i8_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v2.8h, v2.8b, #0
+; CHECK-GI-NEXT: smlal v2.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %tmp1 = sext <8 x i8> %A to <8 x i16>
+ %tmp2 = sext <8 x i8> %B to <8 x i16>
+ %tmp3 = sext <8 x i8> %C to <8 x i16>
+ %tmp4 = mul <8 x i16> %tmp1, %tmp2
+ %tmp5 = add <8 x i16> %tmp4, %tmp3
+ ret <8 x i16> %tmp5
+}
+
+define <8 x i16> @umulladdl_v8i8_v8i16(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-NEON-LABEL: umulladdl_v8i8_v8i16:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: umull v0.8h, v0.8b, v1.8b
+; CHECK-NEON-NEXT: uaddw v0.8h, v0.8h, v2.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: umulladdl_v8i8_v8i16:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: umull v0.8h, v0.8b, v1.8b
+; CHECK-SVE-NEXT: uaddw v0.8h, v0.8h, v2.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: umulladdl_v8i8_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v2.8h, v2.8b, #0
+; CHECK-GI-NEXT: umlal v2.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %tmp1 = zext <8 x i8> %A to <8 x i16>
+ %tmp2 = zext <8 x i8> %B to <8 x i16>
+ %tmp3 = zext <8 x i8> %C to <8 x i16>
+ %tmp4 = mul <8 x i16> %tmp1, %tmp2
+ %tmp5 = add <8 x i16> %tmp4, %tmp3
+ ret <8 x i16> %tmp5
+}
+
+define <8 x i16> @smlall_v8i8_v8i16(<8 x i8> %A, <8 x i8> %B, <8 x i16> %C) nounwind {
+; CHECK-LABEL: smlall_v8i8_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smlal v2.8h, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
+ %tmp1 = sext <8 x i8> %A to <8 x i16>
+ %tmp2 = sext <8 x i8> %B to <8 x i16>
+ %tmp4 = mul <8 x i16> %tmp1, %tmp2
+ %tmp5 = add <8 x i16> %tmp4, %C
+ ret <8 x i16> %tmp5
+}
+
+define <8 x i16> @umlall_v8i8_v8i16(<8 x i8> %A, <8 x i8> %B, <8 x i16> %C) nounwind {
+; CHECK-LABEL: umlall_v8i8_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umlal v2.8h, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
+ %tmp1 = zext <8 x i8> %A to <8 x i16>
+ %tmp2 = zext <8 x i8> %B to <8 x i16>
+ %tmp4 = mul <8 x i16> %tmp1, %tmp2
+ %tmp5 = add <8 x i16> %tmp4, %C
+ ret <8 x i16> %tmp5
+}
+
+define <8 x i16> @smulladdl_const_v8i8_v8i16(<8 x i8> %A, <8 x i8> %C) nounwind {
+; CHECK-NEON-LABEL: smulladdl_const_v8i8_v8i16:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: movi v2.8b, #10
+; CHECK-NEON-NEXT: smull v0.8h, v0.8b, v2.8b
+; CHECK-NEON-NEXT: saddw v0.8h, v0.8h, v1.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: smulladdl_const_v8i8_v8i16:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: movi v2.8b, #10
+; CHECK-SVE-NEXT: smull v0.8h, v0.8b, v2.8b
+; CHECK-SVE-NEXT: saddw v0.8h, v0.8h, v1.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: smulladdl_const_v8i8_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.8h, #10
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: mul v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: saddw v0.8h, v0.8h, v1.8b
+; CHECK-GI-NEXT: ret
+ %tmp1 = sext <8 x i8> %A to <8 x i16>
+ %tmp3 = sext <8 x i8> %C to <8 x i16>
+ %tmp4 = mul <8 x i16> %tmp1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ %tmp5 = add <8 x i16> %tmp4, %tmp3
+ ret <8 x i16> %tmp5
+}
+
+define <8 x i16> @umulladdl_const_v8i8_v8i16(<8 x i8> %A, <8 x i8> %C) nounwind {
+; CHECK-NEON-LABEL: umulladdl_const_v8i8_v8i16:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: movi v2.8b, #10
+; CHECK-NEON-NEXT: umull v0.8h, v0.8b, v2.8b
+; CHECK-NEON-NEXT: uaddw v0.8h, v0.8h, v1.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: umulladdl_const_v8i8_v8i16:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: movi v2.8b, #10
+; CHECK-SVE-NEXT: umull v0.8h, v0.8b, v2.8b
+; CHECK-SVE-NEXT: uaddw v0.8h, v0.8h, v1.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: umulladdl_const_v8i8_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.8h, #10
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: mul v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: uaddw v0.8h, v0.8h, v1.8b
+; CHECK-GI-NEXT: ret
+ %tmp1 = zext <8 x i8> %A to <8 x i16>
+ %tmp3 = zext <8 x i8> %C to <8 x i16>
+ %tmp4 = mul <8 x i16> %tmp1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ %tmp5 = add <8 x i16> %tmp4, %tmp3
+ ret <8 x i16> %tmp5
+}
+
+define <8 x i16> @sdistribute_v8i8(<8 x i8> %src1, <8 x i8> %src2, <8 x i8> %mul) {
+; CHECK-NEON-LABEL: sdistribute_v8i8:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: smull v0.8h, v0.8b, v2.8b
+; CHECK-NEON-NEXT: smlal v0.8h, v1.8b, v2.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: sdistribute_v8i8:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: smull v0.8h, v0.8b, v2.8b
+; CHECK-SVE-NEXT: smlal v0.8h, v1.8b, v2.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: sdistribute_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.8h, v2.8b, #0
+; CHECK-GI-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: mul v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = sext <8 x i8> %src1 to <8 x i16>
+ %5 = sext <8 x i8> %mul to <8 x i16>
+ %7 = sext <8 x i8> %src2 to <8 x i16>
+ %8 = add nuw nsw <8 x i16> %4, %7
+ %9 = mul <8 x i16> %8, %5
+ ret <8 x i16> %9
+}
+
+define <8 x i16> @sdistribute_const1_v8i8(<8 x i8> %src1, <8 x i8> %mul) {
+; CHECK-NEON-LABEL: sdistribute_const1_v8i8:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: movi v2.8b, #10
+; CHECK-NEON-NEXT: smull v0.8h, v0.8b, v1.8b
+; CHECK-NEON-NEXT: smlal v0.8h, v2.8b, v1.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: sdistribute_const1_v8i8:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: movi v2.8b, #10
+; CHECK-SVE-NEXT: smull v0.8h, v0.8b, v1.8b
+; CHECK-SVE-NEXT: smlal v0.8h, v2.8b, v1.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: sdistribute_const1_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8h, #10
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: saddw v0.8h, v2.8h, v0.8b
+; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = sext <8 x i8> %src1 to <8 x i16>
+ %5 = sext <8 x i8> %mul to <8 x i16>
+ %8 = add nuw nsw <8 x i16> %4, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ %9 = mul <8 x i16> %8, %5
+ ret <8 x i16> %9
+}
+
+define <8 x i16> @sdistribute_const2_v8i8(<8 x i8> %src1, <8 x i8> %src2) {
+; CHECK-NEON-LABEL: sdistribute_const2_v8i8:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: movi v2.8b, #10
+; CHECK-NEON-NEXT: smull v0.8h, v0.8b, v2.8b
+; CHECK-NEON-NEXT: smlal v0.8h, v1.8b, v2.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: sdistribute_const2_v8i8:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: movi v2.8b, #10
+; CHECK-SVE-NEXT: smull v0.8h, v0.8b, v2.8b
+; CHECK-SVE-NEXT: smlal v0.8h, v1.8b, v2.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: sdistribute_const2_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8h, #10
+; CHECK-GI-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: mul v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = sext <8 x i8> %src1 to <8 x i16>
+ %5 = sext <8 x i8> %src2 to <8 x i16>
+ %8 = add nuw nsw <8 x i16> %4, %5
+ %9 = mul <8 x i16> %8, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ ret <8 x i16> %9
+}
+
+define <8 x i16> @udistribute_v8i8(<8 x i8> %src1, <8 x i8> %src2, <8 x i8> %mul) {
+; CHECK-NEON-LABEL: udistribute_v8i8:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: umull v0.8h, v0.8b, v2.8b
+; CHECK-NEON-NEXT: umlal v0.8h, v1.8b, v2.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: udistribute_v8i8:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: umull v0.8h, v0.8b, v2.8b
+; CHECK-SVE-NEXT: umlal v0.8h, v1.8b, v2.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: udistribute_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.8h, v2.8b, #0
+; CHECK-GI-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: mul v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = zext <8 x i8> %src1 to <8 x i16>
+ %5 = zext <8 x i8> %mul to <8 x i16>
+ %7 = zext <8 x i8> %src2 to <8 x i16>
+ %8 = add nuw nsw <8 x i16> %4, %7
+ %9 = mul <8 x i16> %8, %5
+ ret <8 x i16> %9
+}
+
+define <8 x i16> @udistribute_const1_v8i8(<8 x i8> %src1, <8 x i8> %mul) {
+; CHECK-NEON-LABEL: udistribute_const1_v8i8:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: movi v2.8b, #10
+; CHECK-NEON-NEXT: umull v0.8h, v0.8b, v1.8b
+; CHECK-NEON-NEXT: umlal v0.8h, v2.8b, v1.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: udistribute_const1_v8i8:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: movi v2.8b, #10
+; CHECK-SVE-NEXT: umull v0.8h, v0.8b, v1.8b
+; CHECK-SVE-NEXT: umlal v0.8h, v2.8b, v1.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: udistribute_const1_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8h, #10
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: uaddw v0.8h, v2.8h, v0.8b
+; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = zext <8 x i8> %src1 to <8 x i16>
+ %5 = zext <8 x i8> %mul to <8 x i16>
+ %8 = add nuw nsw <8 x i16> %4, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ %9 = mul <8 x i16> %8, %5
+ ret <8 x i16> %9
+}
+
+define <8 x i16> @udistribute_const2_v8i8(<8 x i8> %src1, <8 x i8> %src2) {
+; CHECK-NEON-LABEL: udistribute_const2_v8i8:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: movi v2.8b, #10
+; CHECK-NEON-NEXT: umull v0.8h, v0.8b, v2.8b
+; CHECK-NEON-NEXT: umlal v0.8h, v1.8b, v2.8b
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: udistribute_const2_v8i8:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: movi v2.8b, #10
+; CHECK-SVE-NEXT: umull v0.8h, v0.8b, v2.8b
+; CHECK-SVE-NEXT: umlal v0.8h, v1.8b, v2.8b
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: udistribute_const2_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8h, #10
+; CHECK-GI-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: mul v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = zext <8 x i8> %src1 to <8 x i16>
+ %5 = zext <8 x i8> %src2 to <8 x i16>
+ %8 = add nuw nsw <8 x i16> %4, %5
+ %9 = mul <8 x i16> %8, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+ ret <8 x i16> %9
+}
+
+
+define <2 x i64> @smulladdl_v2i32_v2i64(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-NEON-LABEL: smulladdl_v2i32_v2i64:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: smull v0.2d, v0.2s, v1.2s
+; CHECK-NEON-NEXT: saddw v0.2d, v0.2d, v2.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: smulladdl_v2i32_v2i64:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: smull v0.2d, v0.2s, v1.2s
+; CHECK-SVE-NEXT: saddw v0.2d, v0.2d, v2.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: smulladdl_v2i32_v2i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-GI-NEXT: smlal v2.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %tmp1 = sext <2 x i32> %A to <2 x i64>
+ %tmp2 = sext <2 x i32> %B to <2 x i64>
+ %tmp3 = sext <2 x i32> %C to <2 x i64>
+ %tmp4 = mul <2 x i64> %tmp1, %tmp2
+ %tmp5 = add <2 x i64> %tmp4, %tmp3
+ ret <2 x i64> %tmp5
+}
+
+define <2 x i64> @umulladdl_v2i32_v2i64(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-NEON-LABEL: umulladdl_v2i32_v2i64:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-NEON-NEXT: uaddw v0.2d, v0.2d, v2.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: umulladdl_v2i32_v2i64:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-SVE-NEXT: uaddw v0.2d, v0.2d, v2.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: umulladdl_v2i32_v2i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v2.2d, v2.2s, #0
+; CHECK-GI-NEXT: umlal v2.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
+ %tmp1 = zext <2 x i32> %A to <2 x i64>
+ %tmp2 = zext <2 x i32> %B to <2 x i64>
+ %tmp3 = zext <2 x i32> %C to <2 x i64>
+ %tmp4 = mul <2 x i64> %tmp1, %tmp2
+ %tmp5 = add <2 x i64> %tmp4, %tmp3
+ ret <2 x i64> %tmp5
+}
+
+define <2 x i64> @smlall_v2i32_v2i64(<2 x i32> %A, <2 x i32> %B, <2 x i64> %C) nounwind {
+; CHECK-LABEL: smlall_v2i32_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smlal v2.2d, v0.2s, v1.2s
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
+ %tmp1 = sext <2 x i32> %A to <2 x i64>
+ %tmp2 = sext <2 x i32> %B to <2 x i64>
+ %tmp4 = mul <2 x i64> %tmp1, %tmp2
+ %tmp5 = add <2 x i64> %tmp4, %C
+ ret <2 x i64> %tmp5
+}
+
+define <2 x i64> @umlall_v2i32_v2i64(<2 x i32> %A, <2 x i32> %B, <2 x i64> %C) nounwind {
+; CHECK-LABEL: umlall_v2i32_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umlal v2.2d, v0.2s, v1.2s
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
+ %tmp1 = zext <2 x i32> %A to <2 x i64>
+ %tmp2 = zext <2 x i32> %B to <2 x i64>
+ %tmp4 = mul <2 x i64> %tmp1, %tmp2
+ %tmp5 = add <2 x i64> %tmp4, %C
+ ret <2 x i64> %tmp5
+}
+
+define <2 x i64> @smulladdl_const_v2i32_v2i64(<2 x i32> %A, <2 x i32> %C) nounwind {
+; CHECK-NEON-LABEL: smulladdl_const_v2i32_v2i64:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: movi v2.2s, #10
+; CHECK-NEON-NEXT: smull v0.2d, v0.2s, v2.2s
+; CHECK-NEON-NEXT: saddw v0.2d, v0.2d, v1.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: smulladdl_const_v2i32_v2i64:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: movi v2.2s, #10
+; CHECK-SVE-NEXT: smull v0.2d, v0.2s, v2.2s
+; CHECK-SVE-NEXT: saddw v0.2d, v0.2d, v1.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: smulladdl_const_v2i32_v2i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI98_0
+; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI98_0]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v2.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: saddw v0.2d, v0.2d, v1.2s
+; CHECK-GI-NEXT: ret
+ %tmp1 = sext <2 x i32> %A to <2 x i64>
+ %tmp3 = sext <2 x i32> %C to <2 x i64>
+ %tmp4 = mul <2 x i64> %tmp1, <i64 10, i64 10>
+ %tmp5 = add <2 x i64> %tmp4, %tmp3
+ ret <2 x i64> %tmp5
+}
+
+define <2 x i64> @umulladdl_const_v2i32_v2i64(<2 x i32> %A, <2 x i32> %C) nounwind {
+; CHECK-NEON-LABEL: umulladdl_const_v2i32_v2i64:
+; CHECK-NEON: // %bb.0:
+; CHECK-NEON-NEXT: movi v2.2s, #10
+; CHECK-NEON-NEXT: umull v0.2d, v0.2s, v2.2s
+; CHECK-NEON-NEXT: uaddw v0.2d, v0.2d, v1.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: umulladdl_const_v2i32_v2i64:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: movi v2.2s, #10
+; CHECK-SVE-NEXT: umull v0.2d, v0.2s, v2.2s
+; CHECK-SVE-NEXT: uaddw v0.2d, v0.2d, v1.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: umulladdl_const_v2i32_v2i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI99_0
+; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI99_0]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v2.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: uaddw v0.2d, v0.2d, v1.2s
+; CHECK-GI-NEXT: ret
+ %tmp1 = zext <2 x i32> %A to <2 x i64>
+ %tmp3 = zext <2 x i32> %C to <2 x i64>
+ %tmp4 = mul <2 x i64> %tmp1, <i64 10, i64 10>
+ %tmp5 = add <2 x i64> %tmp4, %tmp3
+ ret <2 x i64> %tmp5
+}
+
+define <2 x i64> @sdistribute_v2i32(<2 x i32> %src1, <2 x i32> %src2, <2 x i32> %mul) {
+; CHECK-NEON-LABEL: sdistribute_v2i32:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: smull v0.2d, v0.2s, v2.2s
+; CHECK-NEON-NEXT: smlal v0.2d, v1.2s, v2.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: sdistribute_v2i32:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: smull v0.2d, v0.2s, v2.2s
+; CHECK-SVE-NEXT: smlal v0.2d, v1.2s, v2.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: sdistribute_v2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-GI-NEXT: saddl v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v2.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = sext <2 x i32> %src1 to <2 x i64>
+ %5 = sext <2 x i32> %mul to <2 x i64>
+ %7 = sext <2 x i32> %src2 to <2 x i64>
+ %8 = add nuw nsw <2 x i64> %4, %7
+ %9 = mul <2 x i64> %8, %5
+ ret <2 x i64> %9
+}
+
+define <2 x i64> @sdistribute_const1_v2i32(<2 x i32> %src1, <2 x i32> %mul) {
+; CHECK-NEON-LABEL: sdistribute_const1_v2i32:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: movi v2.2s, #10
+; CHECK-NEON-NEXT: smull v0.2d, v0.2s, v1.2s
+; CHECK-NEON-NEXT: smlal v0.2d, v2.2s, v1.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: sdistribute_const1_v2i32:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: movi v2.2s, #10
+; CHECK-SVE-NEXT: smull v0.2d, v0.2s, v1.2s
+; CHECK-SVE-NEXT: smlal v0.2d, v2.2s, v1.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: sdistribute_const1_v2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI101_0
+; CHECK-GI-NEXT: sshll v1.2d, v1.2s, #0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI101_0]
+; CHECK-GI-NEXT: saddw v0.2d, v2.2d, v0.2s
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: mov x11, v1.d[1]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = sext <2 x i32> %src1 to <2 x i64>
+ %5 = sext <2 x i32> %mul to <2 x i64>
+ %8 = add nuw nsw <2 x i64> %4, <i64 10, i64 10>
+ %9 = mul <2 x i64> %8, %5
+ ret <2 x i64> %9
+}
+
+define <2 x i64> @sdistribute_const2_v2i32(<2 x i32> %src1, <2 x i32> %src2) {
+; CHECK-NEON-LABEL: sdistribute_const2_v2i32:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: movi v2.2s, #10
+; CHECK-NEON-NEXT: smull v0.2d, v0.2s, v2.2s
+; CHECK-NEON-NEXT: smlal v0.2d, v1.2s, v2.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: sdistribute_const2_v2i32:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: movi v2.2s, #10
+; CHECK-SVE-NEXT: smull v0.2d, v0.2s, v2.2s
+; CHECK-SVE-NEXT: smlal v0.2d, v1.2s, v2.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: sdistribute_const2_v2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI102_0
+; CHECK-GI-NEXT: saddl v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI102_0]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v1.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = sext <2 x i32> %src1 to <2 x i64>
+ %5 = sext <2 x i32> %src2 to <2 x i64>
+ %8 = add nuw nsw <2 x i64> %4, %5
+ %9 = mul <2 x i64> %8, <i64 10, i64 10>
+ ret <2 x i64> %9
+}
+
+define <2 x i64> @udistribute_v2i32(<2 x i32> %src1, <2 x i32> %src2, <2 x i32> %mul) {
+; CHECK-NEON-LABEL: udistribute_v2i32:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: umull v0.2d, v0.2s, v2.2s
+; CHECK-NEON-NEXT: umlal v0.2d, v1.2s, v2.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: udistribute_v2i32:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: umull v0.2d, v0.2s, v2.2s
+; CHECK-SVE-NEXT: umlal v0.2d, v1.2s, v2.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: udistribute_v2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.2d, v2.2s, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v2.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = zext <2 x i32> %src1 to <2 x i64>
+ %5 = zext <2 x i32> %mul to <2 x i64>
+ %7 = zext <2 x i32> %src2 to <2 x i64>
+ %8 = add nuw nsw <2 x i64> %4, %7
+ %9 = mul <2 x i64> %8, %5
+ ret <2 x i64> %9
+}
+
+define <2 x i64> @udistribute_const1_v2i32(<2 x i32> %src1, <2 x i32> %mul) {
+; CHECK-NEON-LABEL: udistribute_const1_v2i32:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: movi v2.2s, #10
+; CHECK-NEON-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-NEON-NEXT: umlal v0.2d, v2.2s, v1.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: udistribute_const1_v2i32:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: movi v2.2s, #10
+; CHECK-SVE-NEXT: umull v0.2d, v0.2s, v1.2s
+; CHECK-SVE-NEXT: umlal v0.2d, v2.2s, v1.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: udistribute_const1_v2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI104_0
+; CHECK-GI-NEXT: ushll v1.2d, v1.2s, #0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI104_0]
+; CHECK-GI-NEXT: uaddw v0.2d, v2.2d, v0.2s
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: mov x11, v1.d[1]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = zext <2 x i32> %src1 to <2 x i64>
+ %5 = zext <2 x i32> %mul to <2 x i64>
+ %8 = add nuw nsw <2 x i64> %4, <i64 10, i64 10>
+ %9 = mul <2 x i64> %8, %5
+ ret <2 x i64> %9
+}
+
+define <2 x i64> @udistribute_const2_v2i32(<2 x i32> %src1, <2 x i32> %src2) {
+; CHECK-NEON-LABEL: udistribute_const2_v2i32:
+; CHECK-NEON: // %bb.0: // %entry
+; CHECK-NEON-NEXT: movi v2.2s, #10
+; CHECK-NEON-NEXT: umull v0.2d, v0.2s, v2.2s
+; CHECK-NEON-NEXT: umlal v0.2d, v1.2s, v2.2s
+; CHECK-NEON-NEXT: ret
+;
+; CHECK-SVE-LABEL: udistribute_const2_v2i32:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: movi v2.2s, #10
+; CHECK-SVE-NEXT: umull v0.2d, v0.2s, v2.2s
+; CHECK-SVE-NEXT: umlal v0.2d, v1.2s, v2.2s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-GI-LABEL: udistribute_const2_v2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI105_0
+; CHECK-GI-NEXT: uaddl v0.2d, v0.2s, v1.2s
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI105_0]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: mov x10, v0.d[1]
+; CHECK-GI-NEXT: mov x11, v1.d[1]
+; CHECK-GI-NEXT: mul x8, x8, x9
+; CHECK-GI-NEXT: mul x9, x10, x11
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ret
+entry:
+ %4 = zext <2 x i32> %src1 to <2 x i64>
+ %5 = zext <2 x i32> %src2 to <2 x i64>
+ %8 = add nuw nsw <2 x i64> %4, %5
+ %9 = mul <2 x i64> %8, <i64 10, i64 10>
+ ret <2 x i64> %9
+}
+
declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)
declare <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8>, <8 x i8>)
declare <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8>, <8 x i8>)
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