[llvm] [DAGCombiner] Ensure poison-generating flags are stripped in `freeze` op (PR #114582)

[Yingwei Zheng via llvm-commits]

================
@@ -16151,6 +16151,7 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
                              SVN->getMask());
   } else {
     // NOTE: this strips poison generating flags.
+    N0->dropFlags(SDNodeFlags::PoisonGeneratingFlags);
----------------
dtcxzyw wrote:

baseline: f1e1055c84bb7177f3e7d690442f3760326a0ace
```
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7eef09e55101..b5bc6d925b41 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16150,8 +16150,12 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
     R = DAG.getVectorShuffle(N0.getValueType(), SDLoc(N0), Ops[0], Ops[1],
                              SVN->getMask());
   } else {
+    errs() << "N0: ";
+    N0->dump();
     // NOTE: this strips poison generating flags.
     R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops);
+    errs() << "R: ";
+    R->dump();
   }
   assert(DAG.isGuaranteedNotToBeUndefOrPoison(R, /*PoisonOnly*/ false) &&
          "Can't create node that may be undef/poison!");
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d5cdd7163d79..a533ac910588 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10318,8 +10318,11 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     AddNodeIDNode(ID, Opcode, VTs, Ops);
     void *IP = nullptr;
 
-    if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
+    if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
+      errs() << "E: ";
+      E->dump();
       return SDValue(E, 0);
+    }
 
     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
     createOperands(N, Ops);
```
```
N0: t27: i32 = select_cc samesign t12, t28, t16, t2, setult:ch
E: t27: i32 = select_cc samesign t12, t28, t16, t2, setult:ch
R: t27: i32 = select_cc samesign t12, t28, t16, t2, setult:ch
```

https://github.com/llvm/llvm-project/pull/114582