[llvm] 6365ee8 - [X86][AMX] Move TPAIRS into PositionOrder 3, NFCI (#114642)
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Sat Nov 2 03:14:52 PDT 2024
Author: Phoebe Wang
Date: 2024-11-02T18:14:48+08:00
New Revision: 6365ee884903052d086946bb9f43922743631a4a
URL: https://github.com/llvm/llvm-project/commit/6365ee884903052d086946bb9f43922743631a4a
DIFF: https://github.com/llvm/llvm-project/commit/6365ee884903052d086946bb9f43922743631a4a.diff
LOG: [X86][AMX] Move TPAIRS into PositionOrder 3, NFCI (#114642)
Should solve compile time regression.
Added:
Modified:
llvm/lib/Target/X86/X86RegisterInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 19a0b37d06a2a5..f93f920b6aeca3 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -432,11 +432,11 @@ def TMM4: X86Reg<"tmm4", 4>;
def TMM5: X86Reg<"tmm5", 5>;
def TMM6: X86Reg<"tmm6", 6>;
def TMM7: X86Reg<"tmm7", 7>;
-}
// TMM register pairs
def TPAIRS : RegisterTuples<[sub_t0, sub_t1],
[(add TMM0, TMM2, TMM4, TMM6),
(add TMM1, TMM3, TMM5, TMM7)]>;
+}
// Floating point stack registers. These don't map one-to-one to the FP
// pseudo registers, but we still mark them as aliasing FP registers. That
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