[llvm] [AMDGPU] Extend type support for update_dpp intrinsic (PR #114597)
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Fri Nov 1 12:30:05 PDT 2024
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git-clang-format --diff fe5215281d6304c2b987e0cedc183dbbf8897fcb c7aa15d8ed36704db152e2c923931302ada59d40 --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 410cf98d50..765d9f2f58 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -5537,7 +5537,7 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
if (Size < 32) {
Src0 = B.buildAnyExt(S32, Src0).getReg(0);
- if (IID == Intrinsic::amdgcn_update_dpp ||IsSetInactive || IsPermLane16)
+ if (IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16)
Src1 = B.buildAnyExt(LLT::scalar(32), Src1).getReg(0);
if (IID == Intrinsic::amdgcn_writelane)
@@ -5555,8 +5555,7 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
LLT PartialResTy = LLT::scalar(SplitSize);
if (Ty.isVector()) {
LLT EltTy = Ty.getElementType();
- unsigned EltSize =
- EltTy.getSizeInBits();
+ unsigned EltSize = EltTy.getSizeInBits();
if (EltSize == SplitSize)
PartialResTy = EltTy;
else if (EltSize == 16 || EltSize == 32)
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https://github.com/llvm/llvm-project/pull/114597
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