[llvm] [AArch64] Add assembly/disassembly for FMOP4A (widening, 2-way, FP8 to FP16) instructions (PR #113348)

[via llvm-commits]

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@@ -5188,3 +5188,38 @@ class sme2_luti4_vector_vg4_strided<bits<2> sz, bits<2> op, string mnemonic>
   let Inst{3-2}   = 0b00;
   let Inst{1-0}   = Zd{1-0};
 }
+
+class sme2_fp8_fp16_quarter_tile_outer_product<bit M, bit N, string mnemonic, RegisterOperand zn_ty, RegisterOperand zm_ty>
+    : I<(outs TileOp16:$ZAda),
+        (ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
+        mnemonic, "\t$ZAda, $Zn, $Zm",
+        "", []>, Sched<[]> {
+  bit     ZAda;
+  bits<3> Zn;
+  bits<3> Zm;
+
+  let Inst{31-21} = 0b10000000001;
+  let Inst{20} = M;
+  let Inst{19-17} = Zm;
+  let Inst{16-10} = 0b0000000;
+  let Inst{9} = N;
+  let Inst{8-6} = Zn;
+  let Inst{5-1} = 0b00100;
+  let Inst{0} = ZAda;
+
+  let Constraints = "$ZAda = $_ZAda";
+}
+
+multiclass sme2_fmop4a_fp8_fp16_2way<string mnemonic> {
+  // Single vectors
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CarolineConcatto wrote:

I was not saying it is better for 1 bit. I believe it does not make difference. 
But what I am suggesting is a pattern that I see most often (0b1/0b0) in this file and other related to instruction format.
In the llvm documentation it is also like you wrote for 1 bit:
https://llvm.org/docs/TableGen/ProgRef.html
I was just saying that this is not usually what I see in this file.

https://github.com/llvm/llvm-project/pull/113348