[llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (NFCI) (PR #113903)

[David Green via llvm-commits]

davemgreen wrote:

Hello. I believe the basic patterns are the ones listed in the summary, which are an extended-add-reduction or an extended mla reduction:
```
reduce(ext(...))
reduce.add(mul(...))
reduce.add(mul(ext(...), ext(...)))
```
In the case of MVE, both the ext's will be the same. The add can be done by setting one of the operands to 1. #92418 is similar, but produce a vector instead of a single output value (a dot-product). Dot product has udot, sdot and usdot that do `partialreduce.add(mul(sext, zext))`, but for MVE the extends need to be the same.

There are also other patterns that come up too. The first I believe should be equivalent to `vecreduce(mul(ext, ext))`, providing the ext nodes are the correct types. I don't remember about the second.
```
reduce.add(ext(mul(ext(...), ext(...))))
reduce.add(ext(mul(...)))
```

AArch64 has a stand-alone umull instruction (both for scalar and for vector, although the type sizes differ), that performs a `mul(ext, ext)`. Sometimes it might be better to fold towards `ext(load)` though, depending on the types.

https://github.com/llvm/llvm-project/pull/113903