[llvm] aa70d84 - [GlobalISel][AArch64] Legalize G_SPLAT_VECTOR (#114006)

[via llvm-commits]

Author: Thorsten Schütt
Date: 2024-10-31T22:20:08+01:00
New Revision: aa70d846b0102e62dbfae7e441a3d5d5c906f4b5

URL: https://github.com/llvm/llvm-project/commit/aa70d846b0102e62dbfae7e441a3d5d5c906f4b5
DIFF: https://github.com/llvm/llvm-project/commit/aa70d846b0102e62dbfae7e441a3d5d5c906f4b5.diff

LOG: [GlobalISel][AArch64] Legalize G_SPLAT_VECTOR (#114006)

{nxv8s16, s16} fails to select.
{nxv16s8, s8} no patterns available.

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll

Modified: 
    llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index d1d0c5ff873410..79c07bc2fc9204 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -148,6 +148,7 @@ def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>;
 def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
 def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
 def : GINodeEquiv<G_EXTRACT_SUBVECTOR, extract_subvector>;
+def : GINodeEquiv<G_SPLAT_VECTOR, splat_vector>;
 def : GINodeEquiv<G_FCEIL, fceil>;
 def : GINodeEquiv<G_FCOS, fcos>;
 def : GINodeEquiv<G_FSIN, fsin>;

diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 6024027afaf6ce..400024922124cd 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1316,6 +1316,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .widenScalarOrEltToNextPow2(0)
       .immIdx(0); // Inform verifier imm idx 0 is handled.
 
+  // TODO: {nxv16s8, s8}, {nxv8s16, s16}
+  getActionDefinitionsBuilder(G_SPLAT_VECTOR)
+      .legalFor(HasSVE, {{nxv4s32, s32}, {nxv2s64, s64}});
+
   getLegacyLegalizerInfo().computeTables();
   verify(*ST.getInstrInfo());
 }

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
new file mode 100644
index 00000000000000..0193952aa2ab27
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1  | FileCheck %s  --check-prefixes=CHECK,CHECK-SDAG
+; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GS
+
+; REQUIRES: asserts, aarch64-registered-target
+
+;; add
+define <vscale x 2 x i64> @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-SDAG-LABEL: addnxv2i64:
+; CHECK-SDAG:       // %bb.0: // %entry
+; CHECK-SDAG-NEXT:    add z0.d, z0.d, #9 // =0x9
+; CHECK-SDAG-NEXT:    ret
+;
+; CHECK-GS-LABEL: addnxv2i64:
+; CHECK-GS:       // %bb.0: // %entry
+; CHECK-GS-NEXT:    mov w8, #9 // =0x9
+; CHECK-GS-NEXT:    mov z1.d, x8
+; CHECK-GS-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-GS-NEXT:    ret
+entry:
+  %c = add <vscale x 2 x i64> %a, splat (i64 9)
+  ret <vscale x 2 x i64> %c
+}
+
+define <vscale x 2 x i64> @splarnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-SDAG-LABEL: splarnxv2i64:
+; CHECK-SDAG:       // %bb.0: // %entry
+; CHECK-SDAG-NEXT:    mov z0.d, #9 // =0x9
+; CHECK-SDAG-NEXT:    ret
+;
+; CHECK-GS-LABEL: splarnxv2i64:
+; CHECK-GS:       // %bb.0: // %entry
+; CHECK-GS-NEXT:    mov w8, #9 // =0x9
+; CHECK-GS-NEXT:    mov z0.d, x8
+; CHECK-GS-NEXT:    ret
+entry:
+  ret <vscale x 2 x i64> splat (i64 9)
+}
+
+define <vscale x 4 x i32> @addnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-SDAG-LABEL: addnxv4i32:
+; CHECK-SDAG:       // %bb.0: // %entry
+; CHECK-SDAG-NEXT:    add z0.s, z0.s, #9 // =0x9
+; CHECK-SDAG-NEXT:    ret
+;
+; CHECK-GS-LABEL: addnxv4i32:
+; CHECK-GS:       // %bb.0: // %entry
+; CHECK-GS-NEXT:    mov w8, #9 // =0x9
+; CHECK-GS-NEXT:    mov z1.s, w8
+; CHECK-GS-NEXT:    add z0.s, z0.s, z1.s
+; CHECK-GS-NEXT:    ret
+entry:
+  %c = add <vscale x 4 x i32> %a, splat (i32 9)
+  ret <vscale x 4 x i32> %c
+}
+
+define <vscale x 4 x i32> @splatnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-SDAG-LABEL: splatnxv4i32:
+; CHECK-SDAG:       // %bb.0: // %entry
+; CHECK-SDAG-NEXT:    mov z0.s, #9 // =0x9
+; CHECK-SDAG-NEXT:    ret
+;
+; CHECK-GS-LABEL: splatnxv4i32:
+; CHECK-GS:       // %bb.0: // %entry
+; CHECK-GS-NEXT:    mov w8, #9 // =0x9
+; CHECK-GS-NEXT:    mov z0.s, w8
+; CHECK-GS-NEXT:    ret
+entry:
+  ret <vscale x 4 x i32> splat (i32 9)
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}