[llvm] [TableGen] Fix concatenation of subreg and artificial subregs (PR #114391)

[Sander de Smalen via llvm-commits]

sdesmalen-arm wrote:

> > This happens for example when a 64-bit register 'D0' consists of
> > 32-bit 'S0_HI' (artificial) and 'S0', and 'S0' consists of (16-bit)
> > 'H0_HI' (artificial) and 'H0'. Then the concatenation should be:
> > S0_HI, H0_HI, H0.
> 
> But that's not what your patch does, is it? The `Parts` vector only accumulates non-artificial indices (H0 in your example) and then you bail out because `Parts` only contains one part, so no concatenation is recorded.

You're right, the commit message was rubbish. I've updated it, hopefully it makes more sense now.

https://github.com/llvm/llvm-project/pull/114391