[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[via llvm-commits]

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@@ -331,6 +331,9 @@ enum OperandType : unsigned {
   OPERAND_RVKRNUM_2_14,
   OPERAND_SPIMM,
   OPERAND_LAST_RISCV_IMM = OPERAND_SPIMM,
+  // Operand is a 3-bit rounding mode, '111' indicates FRM register.
+  // Represents 'frm' argument passing to floating-point operations.
+  OPERAND_FRMARG,
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AnastasiyaChernikova wrote:

Addressed

https://github.com/llvm/llvm-project/pull/89047