[llvm] [AArch64][SVE] Add codegen support for partial reduction lowering to wide add instructions (PR #114406)

[Benjamin Maxwell via llvm-commits]

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@@ -2042,7 +2042,8 @@ bool AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(
 
   EVT VT = EVT::getEVT(I->getType());
   return VT != MVT::nxv4i64 && VT != MVT::nxv4i32 && VT != MVT::nxv2i64 &&
-         VT != MVT::v4i64 && VT != MVT::v4i32 && VT != MVT::v2i32;
+         VT != MVT::nxv8i16 && VT != MVT::v4i64 && VT != MVT::v4i32 &&
+         VT != MVT::v2i32 && VT != MVT::v8i16;
 }
----------------
MacDue wrote:

I know this was already like this, but I feel like an `is_contained()` check would be more readable than these big expressions :thinking:  
```c++
  EVT VT = EVT::getEVT(I->getType());
  return !is_contained<EVT>({MVT::nxv4i64, MVT::nxv4i32, MVT::nxv2i64,
                             MVT::nxv8i16, MVT::v4i64, MVT::v4i32, MVT::v2i32,
                             MVT::v8i16},
                            VT);
```

https://github.com/llvm/llvm-project/pull/114406