[llvm] 41448c1 - [AArch64] NFC: Add RUN line for +sve2 for sve-intrinsics-perm-select.ll
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 31 07:46:15 PDT 2024
Author: Sander de Smalen
Date: 2024-10-31T14:46:00Z
New Revision: 41448c1d07f25e60c5014dd71d328596fcb5589e
URL: https://github.com/llvm/llvm-project/commit/41448c1d07f25e60c5014dd71d328596fcb5589e
DIFF: https://github.com/llvm/llvm-project/commit/41448c1d07f25e60c5014dd71d328596fcb5589e.diff
LOG: [AArch64] NFC: Add RUN line for +sve2 for sve-intrinsics-perm-select.ll
The codegen for SVE and SVE2 may be different (e.g. for splice and ext).
A follow-up patch will improve codegen for EXT.
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
index 7d81ebaefddb85..fec255b712441e 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK,SVE
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s --check-prefixes=CHECK,SVE2
;
; CLASTA (Vectors)
@@ -570,13 +571,21 @@ define <vscale x 2 x double> @dupq_lane_f64(<vscale x 2 x double> %a, i64 %idx)
; NOTE: Index out of range (0-3)
define <vscale x 2 x i64> @dupq_i64_range(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: dupq_i64_range:
-; CHECK: // %bb.0:
-; CHECK-NEXT: index z1.d, #0, #1
-; CHECK-NEXT: and z1.d, z1.d, #0x1
-; CHECK-NEXT: orr z1.d, z1.d, #0x8
-; CHECK-NEXT: tbl z0.d, { z0.d }, z1.d
-; CHECK-NEXT: ret
+; SVE-LABEL: dupq_i64_range:
+; SVE: // %bb.0:
+; SVE-NEXT: index z1.d, #0, #1
+; SVE-NEXT: and z1.d, z1.d, #0x1
+; SVE-NEXT: orr z1.d, z1.d, #0x8
+; SVE-NEXT: tbl z0.d, { z0.d }, z1.d
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: dupq_i64_range:
+; SVE2: // %bb.0:
+; SVE2-NEXT: index z1.d, #0, #1
+; SVE2-NEXT: and z1.d, z1.d, #0x1
+; SVE2-NEXT: add z1.d, z1.d, #8 // =0x8
+; SVE2-NEXT: tbl z0.d, { z0.d }, z1.d
+; SVE2-NEXT: ret
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %a, i64 4)
ret <vscale x 2 x i64> %out
}
@@ -1082,10 +1091,17 @@ define <vscale x 2 x double> @rev_f64(<vscale x 2 x double> %a) {
;
define <vscale x 16 x i8> @splice_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; CHECK-LABEL: splice_i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b
-; CHECK-NEXT: ret
+; SVE-LABEL: splice_i8:
+; SVE: // %bb.0:
+; SVE-NEXT: splice z0.b, p0, z0.b, z1.b
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: splice_i8:
+; SVE2: // %bb.0:
+; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: splice z0.b, p0, { z0.b, z1.b }
+; SVE2-NEXT: ret
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %pg,
<vscale x 16 x i8> %a,
<vscale x 16 x i8> %b)
@@ -1093,10 +1109,17 @@ define <vscale x 16 x i8> @splice_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8>
}
define <vscale x 8 x i16> @splice_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
-; CHECK-LABEL: splice_i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
-; CHECK-NEXT: ret
+; SVE-LABEL: splice_i16:
+; SVE: // %bb.0:
+; SVE-NEXT: splice z0.h, p0, z0.h, z1.h
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: splice_i16:
+; SVE2: // %bb.0:
+; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: splice z0.h, p0, { z0.h, z1.h }
+; SVE2-NEXT: ret
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %pg,
<vscale x 8 x i16> %a,
<vscale x 8 x i16> %b)
@@ -1104,10 +1127,17 @@ define <vscale x 8 x i16> @splice_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16>
}
define <vscale x 4 x i32> @splice_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-; CHECK-LABEL: splice_i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-NEXT: ret
+; SVE-LABEL: splice_i32:
+; SVE: // %bb.0:
+; SVE-NEXT: splice z0.s, p0, z0.s, z1.s
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: splice_i32:
+; SVE2: // %bb.0:
+; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: splice z0.s, p0, { z0.s, z1.s }
+; SVE2-NEXT: ret
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %pg,
<vscale x 4 x i32> %a,
<vscale x 4 x i32> %b)
@@ -1115,10 +1145,17 @@ define <vscale x 4 x i32> @splice_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32>
}
define <vscale x 2 x i64> @splice_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: splice_i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
-; CHECK-NEXT: ret
+; SVE-LABEL: splice_i64:
+; SVE: // %bb.0:
+; SVE-NEXT: splice z0.d, p0, z0.d, z1.d
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: splice_i64:
+; SVE2: // %bb.0:
+; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: splice z0.d, p0, { z0.d, z1.d }
+; SVE2-NEXT: ret
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %pg,
<vscale x 2 x i64> %a,
<vscale x 2 x i64> %b)
@@ -1126,10 +1163,17 @@ define <vscale x 2 x i64> @splice_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64>
}
define <vscale x 8 x bfloat> @splice_bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
-; CHECK-LABEL: splice_bf16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
-; CHECK-NEXT: ret
+; SVE-LABEL: splice_bf16:
+; SVE: // %bb.0:
+; SVE-NEXT: splice z0.h, p0, z0.h, z1.h
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: splice_bf16:
+; SVE2: // %bb.0:
+; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: splice z0.h, p0, { z0.h, z1.h }
+; SVE2-NEXT: ret
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.splice.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a,
<vscale x 8 x bfloat> %b)
@@ -1137,10 +1181,17 @@ define <vscale x 8 x bfloat> @splice_bf16(<vscale x 8 x i1> %pg, <vscale x 8 x b
}
define <vscale x 8 x half> @splice_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: splice_f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
-; CHECK-NEXT: ret
+; SVE-LABEL: splice_f16:
+; SVE: // %bb.0:
+; SVE-NEXT: splice z0.h, p0, z0.h, z1.h
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: splice_f16:
+; SVE2: // %bb.0:
+; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: splice z0.h, p0, { z0.h, z1.h }
+; SVE2-NEXT: ret
%out = call <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1> %pg,
<vscale x 8 x half> %a,
<vscale x 8 x half> %b)
@@ -1148,10 +1199,17 @@ define <vscale x 8 x half> @splice_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half
}
define <vscale x 4 x float> @splice_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: splice_f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-NEXT: ret
+; SVE-LABEL: splice_f32:
+; SVE: // %bb.0:
+; SVE-NEXT: splice z0.s, p0, z0.s, z1.s
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: splice_f32:
+; SVE2: // %bb.0:
+; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: splice z0.s, p0, { z0.s, z1.s }
+; SVE2-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.splice.nxv4f32(<vscale x 4 x i1> %pg,
<vscale x 4 x float> %a,
<vscale x 4 x float> %b)
@@ -1159,10 +1217,17 @@ define <vscale x 4 x float> @splice_f32(<vscale x 4 x i1> %pg, <vscale x 4 x flo
}
define <vscale x 2 x double> @splice_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: splice_f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
-; CHECK-NEXT: ret
+; SVE-LABEL: splice_f64:
+; SVE: // %bb.0:
+; SVE-NEXT: splice z0.d, p0, z0.d, z1.d
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: splice_f64:
+; SVE2: // %bb.0:
+; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; SVE2-NEXT: splice z0.d, p0, { z0.d, z1.d }
+; SVE2-NEXT: ret
%out = call <vscale x 2 x double> @llvm.aarch64.sve.splice.nxv2f64(<vscale x 2 x i1> %pg,
<vscale x 2 x double> %a,
<vscale x 2 x double> %b)
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