[llvm] [AArch64][SVE] Add codegen support for partial reduction lowering to wide add instructions (PR #114406)

[Graham Hunter via llvm-commits]

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@@ -2042,7 +2042,8 @@ bool AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(
 
   EVT VT = EVT::getEVT(I->getType());
   return VT != MVT::nxv4i64 && VT != MVT::nxv4i32 && VT != MVT::nxv2i64 &&
-         VT != MVT::v4i64 && VT != MVT::v4i32 && VT != MVT::v2i32;
+         VT != MVT::nxv8i16 && VT != MVT::v4i64 && VT != MVT::v4i32 &&
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huntergr-arm wrote:

I think we may want to start looking at the inputs at this point, as the types that we have instructions for differ based on the chain of operations on the second operand. May be something for a follow-up patch.

https://github.com/llvm/llvm-project/pull/114406