[llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

[Sander de Smalen via llvm-commits]

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@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
   return {};
 }
 
+static SmallVector<MCPhysReg> ReservedHi = {
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sdesmalen-arm wrote:

> Alternatively could introduce a new register class for the synthetic cases.

That's actually something I had to do (see [here](https://github.com/llvm/llvm-project/pull/114263/files#diff-bb09862d7b3b9ada050130023cd0b1c537a0560d06c80de744bf63c440139c74R1968-R1976)), as the compiler otherwise runs into some assertion requiring the (artificial) registers to have a corresponding regclass.

> It might also be possible to get away without explicitly marking these as reserved

When I remove these from the list of reserved registers, a lot of the tests fail.

https://github.com/llvm/llvm-project/pull/114263