[llvm] [AArch64][ELF] Section alignment of 4 for AArch64 instruction (PR #114031)
Florin Popa via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 31 04:12:54 PDT 2024
https://github.com/popaflorin updated https://github.com/llvm/llvm-project/pull/114031
>From f9e526c76673e3c4528d3b19eab81a91d2178593 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 1/2] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/MC/MCParser/ELFAsmParser.cpp | 9 ++++++++
.../directive-arch-section-alignment.s | 22 +++++++++++++++++++
2 files changed, 31 insertions(+)
create mode 100644 llvm/test/MC/AArch64/directive-arch-section-alignment.s
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index c4536441665fa0..8e7256d6fae9cd 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -697,6 +697,15 @@ bool ELFAsmParser::ParseSectionArguments(bool IsPush, SMLoc loc) {
getContext().getELFSection(SectionName, Type, Flags, Size, GroupName,
IsComdat, UniqueID, LinkedToSym);
getStreamer().switchSection(Section, Subsection);
+
+ // Section alignment of 4 if an AArch64 instruction is used when $x mapping
+ // symbol is added Match GNU Assembler
+ const Triple &TT = getContext().getTargetTriple();
+ if ((Section->getFlags() & ELF::SHF_EXECINSTR) && (TT.isAArch64())) {
+ if (Section->getAlign() < 4)
+ getStreamer().emitValueToAlignment(Align(4));
+ }
+
// Check that flags are used consistently. However, the GNU assembler permits
// to leave out in subsequent uses of the same sections; for compatibility,
// do likewise.
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
new file mode 100644
index 00000000000000..bf3881b9c288a7
--- /dev/null
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -0,0 +1,22 @@
+// RUN: llvm-mc -triple aarch64-- -o - %s | FileCheck %s
+
+// CHECK: .section sec00
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: nop
+.section sec00, "ax"
+nop
+nop
+// CHECK: .section sec01
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: nop
+.section sec01, "ax"
+.balign 4
+nop
+// CHECK: .section sec02
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: .byte 1
+.section sec02, "ax"
+// CHECK-NEXT: nop
+.byte 1
+nop
>From beb10570240460c24f59cc3360afde67a61f5872 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 2/2] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/MC/MCParser/ELFAsmParser.cpp | 8 ------
.../MCTargetDesc/AArch64ELFStreamer.cpp | 6 +++++
.../directive-arch-section-alignment.s | 27 +++++++++----------
3 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index 8e7256d6fae9cd..67b043b51c62c0 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -698,14 +698,6 @@ bool ELFAsmParser::ParseSectionArguments(bool IsPush, SMLoc loc) {
IsComdat, UniqueID, LinkedToSym);
getStreamer().switchSection(Section, Subsection);
- // Section alignment of 4 if an AArch64 instruction is used when $x mapping
- // symbol is added Match GNU Assembler
- const Triple &TT = getContext().getTargetTriple();
- if ((Section->getFlags() & ELF::SHF_EXECINSTR) && (TT.isAArch64())) {
- if (Section->getAlign() < 4)
- getStreamer().emitValueToAlignment(Align(4));
- }
-
// Check that flags are used consistently. However, the GNU assembler permits
// to leave out in subsequent uses of the same sections; for compatibility,
// do likewise.
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index 490efb650d5038..e15a9237cda1d4 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -202,6 +202,12 @@ class AArch64ELFStreamer : public MCELFStreamer {
LastEMS = EMS_None;
MCELFStreamer::changeSection(Section, Subsection);
+
+ // Section alignment of 4 to match GNU Assembler
+ if (Section->getAlign() < 4) {
+ Section->setAlignment(Align(4));
+ emitValueToAlignment(Align(4), 0, 1, 0);
+ }
}
// Reset state between object emissions
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index bf3881b9c288a7..0c483a8817b20b 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,22 +1,21 @@
-// RUN: llvm-mc -triple aarch64-- -o - %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
+// RUN: llvm-objdump -d -r %t.obj | FileCheck %s
-// CHECK: .section sec00
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: nop
.section sec00, "ax"
nop
nop
-// CHECK: .section sec01
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: nop
+nop
.section sec01, "ax"
.balign 4
nop
-// CHECK: .section sec02
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: .byte 1
-.section sec02, "ax"
-// CHECK-NEXT: nop
-.byte 1
nop
+nop
+
+// CHECK: 0000000000000000 <sec00>:
+// CHECK-NEXT: 0: d503201f nop
+// CHECK-NEXT: 4: d503201f nop
+// CHECK-NEXT: 8: d503201f nop
+// CHECK: 0000000000000000 <sec01>:
+// CHECK-NEXT: 0: d503201f nop
+// CHECK-NEXT: 4: d503201f nop
+// CHECK-NEXT: 8: d503201f nop
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