[llvm] [RISCV] Remove redundant SDNode creation for same reg class value (PR #114348)

[Craig Topper via llvm-commits]

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@@ -21345,18 +21345,17 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
   }
 
   if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
+#ifndef NDEBUG
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topperc wrote:

If the types don't match then I think we need some operation to represent the type change. So I guess the original code is correct.

https://github.com/llvm/llvm-project/pull/114348