[llvm] [GlobalISel][AArch64] Legalize G_SPLAT_VECTOR (PR #114006)
Thorsten Schütt via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 30 21:19:43 PDT 2024
https://github.com/tschuett updated https://github.com/llvm/llvm-project/pull/114006
>From 571bc64562b94ff94c47b5c5ef019b06bca36c89 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Tue, 29 Oct 2024 07:09:03 +0100
Subject: [PATCH 1/6] [GlobalISel][AArch64] Legalize G_SPLAT_VECTOR
---
.../Target/GlobalISel/SelectionDAGCompat.td | 1 +
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 4 +
.../GlobalISel/legalize-splat-vector.mir | 143 ++++++++++++++++++
3 files changed, 148 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index d1d0c5ff873410..79c07bc2fc9204 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -148,6 +148,7 @@ def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>;
def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
def : GINodeEquiv<G_EXTRACT_SUBVECTOR, extract_subvector>;
+def : GINodeEquiv<G_SPLAT_VECTOR, splat_vector>;
def : GINodeEquiv<G_FCEIL, fceil>;
def : GINodeEquiv<G_FCOS, fcos>;
def : GINodeEquiv<G_FSIN, fsin>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 6024027afaf6ce..6f48dd56d1cba9 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1316,6 +1316,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarOrEltToNextPow2(0)
.immIdx(0); // Inform verifier imm idx 0 is handled.
+ // TODO: {nxv8s16, s16}
+ getActionDefinitionsBuilder(G_SPLAT_VECTOR)
+ .legalFor(HasSVE, {{nxv4s32, s32}, {nxv2s64, s64}});
+
getLegacyLegalizerInfo().computeTables();
verify(*ST.getInstrInfo());
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
new file mode 100644
index 00000000000000..1b9e4132a40751
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
@@ -0,0 +1,143 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -debug -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SELECT
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=regbankselect %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-REGBANK
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LEGAL
+
+
+---
+name: test_splat_vector_s64
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s64
+ ; CHECK-SELECT: %imm:gpr64sp = COPY $x0
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64
+ ; CHECK-REGBANK: %imm:gpr(s64) = COPY $x0
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s64
+ ; CHECK-LEGAL: %imm:_(s64) = COPY $x0
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ %imm:_(s64) = COPY $x0
+ %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ $z0 = COPY %splat(<vscale x 2 x s64>)
+...
+---
+name: test_splat_vector_s64_const
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s64_const
+ ; CHECK-SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 9
+ ; CHECK-SELECT-NEXT: %imm:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_const
+ ; CHECK-REGBANK: %imm:gpr(s64) = G_CONSTANT i64 9
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s64_const
+ ; CHECK-LEGAL: %imm:_(s64) = G_CONSTANT i64 9
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ %imm:_(s64) = G_CONSTANT i64 9
+ %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ $z0 = COPY %splat(<vscale x 2 x s64>)
+...
+---
+name: test_splat_vector_s64_fconst
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s64_fconst
+ ; CHECK-SELECT: %imm:fpr64 = FMOVDi 34
+ ; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY %imm
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D [[COPY]]
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_fconst
+ ; CHECK-REGBANK: %imm:fpr(s64) = G_FCONSTANT double 9.000000e+00
+ ; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY %imm(s64)
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[COPY]](s64)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s64_fconst
+ ; CHECK-LEGAL: %imm:_(s64) = G_FCONSTANT double 9.000000e+00
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ %imm:_(s64) = G_FCONSTANT double 9.0
+ %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ $z0 = COPY %splat(<vscale x 2 x s64>)
+...
+---
+name: test_splat_vector_s32
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s32
+ ; CHECK-SELECT: %imm:gpr32sp = COPY $w0
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32
+ ; CHECK-REGBANK: %imm:gpr(s32) = COPY $w0
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s32
+ ; CHECK-LEGAL: %imm:_(s32) = COPY $w0
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ %imm:_(s32) = COPY $w0
+ %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ $z0 = COPY %splat(<vscale x 4 x s32>)
+...
+---
+name: test_splat_vector_s32_const
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s32_const
+ ; CHECK-SELECT: %imm:gpr32common = MOVi32imm 9
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_const
+ ; CHECK-REGBANK: %imm:gpr(s32) = G_CONSTANT i32 9
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s32_const
+ ; CHECK-LEGAL: %imm:_(s32) = G_CONSTANT i32 9
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ %imm:_(s32) = G_CONSTANT i32 9
+ %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ $z0 = COPY %splat(<vscale x 4 x s32>)
+...
+---
+name: test_splat_vector_s32_fconst
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s32_fconst
+ ; CHECK-SELECT: %imm:fpr32 = FMOVSi 28
+ ; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY %imm
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S [[COPY]]
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_fconst
+ ; CHECK-REGBANK: %imm:fpr(s32) = G_FCONSTANT float 7.000000e+00
+ ; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %imm(s32)
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[COPY]](s32)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s32_fconst
+ ; CHECK-LEGAL: %imm:_(s32) = G_FCONSTANT float 7.000000e+00
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ %imm:_(s32) = G_FCONSTANT float 7.0
+ %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ $z0 = COPY %splat(<vscale x 4 x s32>)
+...
>From eb11999b76b593ff639362b5510657bae9b77f4d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Tue, 29 Oct 2024 10:25:52 +0100
Subject: [PATCH 2/6] address review comments
---
.../AArch64/GlobalISel/select-splat-vector.ll | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
new file mode 100644
index 00000000000000..d85fbbfb76793b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-SDAG
+; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GS
+
+;; add
+define <vscale x 2 x i64> @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-SDAG-LABEL: addnxv2i64:
+; CHECK-SDAG: // %bb.0: // %entry
+; CHECK-SDAG-NEXT: add z0.d, z0.d, #9 // =0x9
+; CHECK-SDAG-NEXT: ret
+;
+; CHECK-GS-LABEL: addnxv2i64:
+; CHECK-GS: // %bb.0: // %entry
+; CHECK-GS-NEXT: mov w8, #9 // =0x9
+; CHECK-GS-NEXT: mov z1.d, x8
+; CHECK-GS-NEXT: add z0.d, z0.d, z1.d
+; CHECK-GS-NEXT: ret
+entry:
+ %c = add <vscale x 2 x i64> %a, splat (i64 9)
+ ret <vscale x 2 x i64> %c
+}
+
+define <vscale x 4 x i32> @addnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-SDAG-LABEL: addnxv4i32:
+; CHECK-SDAG: // %bb.0: // %entry
+; CHECK-SDAG-NEXT: add z0.s, z0.s, #9 // =0x9
+; CHECK-SDAG-NEXT: ret
+;
+; CHECK-GS-LABEL: addnxv4i32:
+; CHECK-GS: // %bb.0: // %entry
+; CHECK-GS-NEXT: mov w8, #9 // =0x9
+; CHECK-GS-NEXT: mov z1.s, w8
+; CHECK-GS-NEXT: add z0.s, z0.s, z1.s
+; CHECK-GS-NEXT: ret
+entry:
+ %c = add <vscale x 4 x i32> %a, splat (i32 9)
+ ret <vscale x 4 x i32> %c
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
>From 20eb99752f72816423d59c82abaf6778c5c3b694 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Tue, 29 Oct 2024 12:07:57 +0100
Subject: [PATCH 3/6] remove -debug
---
llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
index 1b9e4132a40751..1384b3b8711dfb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -debug -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SELECT
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SELECT
# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=regbankselect %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-REGBANK
# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LEGAL
>From fd1afc5efebde73d388dfa94c0a1cb658a069902 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Tue, 29 Oct 2024 14:57:51 +0100
Subject: [PATCH 4/6] extend comment
---
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 6f48dd56d1cba9..400024922124cd 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1316,7 +1316,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarOrEltToNextPow2(0)
.immIdx(0); // Inform verifier imm idx 0 is handled.
- // TODO: {nxv8s16, s16}
+ // TODO: {nxv16s8, s8}, {nxv8s16, s16}
getActionDefinitionsBuilder(G_SPLAT_VECTOR)
.legalFor(HasSVE, {{nxv4s32, s32}, {nxv2s64, s64}});
>From 33c85037f4cf6d7f25175942bb467bb7d503e8ca Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Wed, 30 Oct 2024 14:42:19 +0100
Subject: [PATCH 5/6] rebuild legalize splat vector test
---
llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
index 1384b3b8711dfb..10c4693f81ec5b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
@@ -3,7 +3,6 @@
# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=regbankselect %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-REGBANK
# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LEGAL
-
---
name: test_splat_vector_s64
body: |
>From e858db7b4e66f6ad1dfde35a651fcfea0ad88c1d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Thu, 31 Oct 2024 05:19:01 +0100
Subject: [PATCH 6/6] address review comments
---
.../AArch64/GlobalISel/select-splat-vector.ll | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
index d85fbbfb76793b..ce9b67f4c529f8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
@@ -20,6 +20,21 @@ entry:
ret <vscale x 2 x i64> %c
}
+define <vscale x 2 x i64> @splarnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-SDAG-LABEL: splarnxv2i64:
+; CHECK-SDAG: // %bb.0: // %entry
+; CHECK-SDAG-NEXT: mov z0.d, #9 // =0x9
+; CHECK-SDAG-NEXT: ret
+;
+; CHECK-GS-LABEL: splarnxv2i64:
+; CHECK-GS: // %bb.0: // %entry
+; CHECK-GS-NEXT: mov w8, #9 // =0x9
+; CHECK-GS-NEXT: mov z0.d, x8
+; CHECK-GS-NEXT: ret
+entry:
+ ret <vscale x 2 x i64> splat (i64 9)
+}
+
define <vscale x 4 x i32> @addnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-SDAG-LABEL: addnxv4i32:
; CHECK-SDAG: // %bb.0: // %entry
@@ -37,5 +52,20 @@ entry:
ret <vscale x 4 x i32> %c
}
+define <vscale x 4 x i32> @splatnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-SDAG-LABEL: splatnxv4i32:
+; CHECK-SDAG: // %bb.0: // %entry
+; CHECK-SDAG-NEXT: mov z0.s, #9 // =0x9
+; CHECK-SDAG-NEXT: ret
+;
+; CHECK-GS-LABEL: splatnxv4i32:
+; CHECK-GS: // %bb.0: // %entry
+; CHECK-GS-NEXT: mov w8, #9 // =0x9
+; CHECK-GS-NEXT: mov z0.s, w8
+; CHECK-GS-NEXT: ret
+entry:
+ ret <vscale x 4 x i32> splat (i32 9)
+}
+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}
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