[llvm] [RISCV] Remove redundant SDNode creation for same reg class value (PR #114348)

[Brandon Wu via llvm-commits]

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/114348

None

>From 1c5f9eb9af88e4d599570f0e2b1f05b5fd7671dd Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 30 Oct 2024 20:47:21 -0700
Subject: [PATCH] [RISCV] Remove redundant SDNode creation for same reg class
 value

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index af7a39b2580a37..43de3d65de986c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21345,6 +21345,7 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
   }
 
   if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
+#ifndef NDEBUG
     unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
     [[maybe_unused]] unsigned ValLMUL =
         divideCeil(ValueVT.getSizeInBits(), ValNF * RISCV::RVVBitsPerBlock);
@@ -21352,11 +21353,9 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
     [[maybe_unused]] unsigned PartLMUL =
         divideCeil(PartVT.getSizeInBits(), PartNF * RISCV::RVVBitsPerBlock);
     assert(ValNF == PartNF && ValLMUL == PartLMUL &&
-           "RISC-V vector tuple type only accepts same register class type "
-           "TUPLE_INSERT");
+           "RISC-V vector tuple type only accepts same register class copy");
+#endif
 
-    Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
-                      Val, DAG.getVectorIdxConstant(0, DL));
     Parts[0] = Val;
     return true;
   }