[llvm] 55dbacb - [RISCV] Remove RISCVISD::VFCVT_X(U)_F_VL by using VFCVT_RM_X(U)_F_VL with DYN rounding mode. NFC (#114306)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 30 19:16:26 PDT 2024
Author: Craig Topper
Date: 2024-10-30T19:16:23-07:00
New Revision: 55dbacbf0746afa243224b58d4b5f86d3b54774e
URL: https://github.com/llvm/llvm-project/commit/55dbacbf0746afa243224b58d4b5f86d3b54774e
DIFF: https://github.com/llvm/llvm-project/commit/55dbacbf0746afa243224b58d4b5f86d3b54774e.diff
LOG: [RISCV] Remove RISCVISD::VFCVT_X(U)_F_VL by using VFCVT_RM_X(U)_F_VL with DYN rounding mode. NFC (#114306)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e7898747fcce90..0b5c46f2c370c1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3030,6 +3030,7 @@ static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
case ISD::VP_FROUND:
return RISCVFPRndMode::RMM;
case ISD::FRINT:
+ case ISD::VP_FRINT:
return RISCVFPRndMode::DYN;
}
@@ -3101,6 +3102,8 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
switch (Op.getOpcode()) {
default:
llvm_unreachable("Unexpected opcode");
+ case ISD::FRINT:
+ case ISD::VP_FRINT:
case ISD::FCEIL:
case ISD::VP_FCEIL:
case ISD::FFLOOR:
@@ -3120,10 +3123,6 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
Truncated = DAG.getNode(RISCVISD::VFCVT_RTZ_X_F_VL, DL, IntVT, Src,
Mask, VL);
break;
- case ISD::FRINT:
- case ISD::VP_FRINT:
- Truncated = DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, IntVT, Src, Mask, VL);
- break;
case ISD::FNEARBYINT:
case ISD::VP_FNEARBYINT:
Truncated = DAG.getNode(RISCVISD::VFROUND_NOEXCEPT_VL, DL, ContainerVT, Src,
@@ -3294,8 +3293,10 @@ static SDValue lowerVectorXRINT(SDValue Op, SelectionDAG &DAG,
}
auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
- SDValue Truncated =
- DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, ContainerVT, Src, Mask, VL);
+ SDValue Truncated = DAG.getNode(
+ RISCVISD::VFCVT_RM_X_F_VL, DL, ContainerVT, Src, Mask,
+ DAG.getTargetConstant(RISCVFPRndMode::DYN, DL, Subtarget.getXLenVT()),
+ VL);
if (!VT.isFixedLengthVector())
return Truncated;
@@ -6166,7 +6167,7 @@ static unsigned getRISCVVLOp(SDValue Op) {
case ISD::VP_LRINT:
case ISD::LLRINT:
case ISD::VP_LLRINT:
- return RISCVISD::VFCVT_X_F_VL;
+ return RISCVISD::VFCVT_RM_X_F_VL;
}
// clang-format on
#undef OP_CASE
@@ -6179,7 +6180,7 @@ static bool hasPassthruOp(unsigned Opcode) {
Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE &&
"not a RISC-V target specific op");
static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP ==
- 130 &&
+ 128 &&
RISCVISD::LAST_RISCV_STRICTFP_OPCODE -
ISD::FIRST_TARGET_STRICTFP_OPCODE ==
21 &&
@@ -6205,7 +6206,7 @@ static bool hasMaskOp(unsigned Opcode) {
Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE &&
"not a RISC-V target specific op");
static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP ==
- 130 &&
+ 128 &&
RISCVISD::LAST_RISCV_STRICTFP_OPCODE -
ISD::FIRST_TARGET_STRICTFP_OPCODE ==
21 &&
@@ -11545,6 +11546,11 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const {
}
}
}
+ // VFCVT_RM_X_F_VL requires a rounding mode to be injected before the VL.
+ if (RISCVISDOpc == RISCVISD::VFCVT_RM_X_F_VL &&
+ ISD::getVPExplicitVectorLengthIdx(Op.getOpcode()) == OpIdx.index())
+ Ops.push_back(DAG.getTargetConstant(RISCVFPRndMode::DYN, DL,
+ Subtarget.getXLenVT()));
// Pass through operands which aren't fixed-length vectors.
if (!V.getValueType().isFixedLengthVector()) {
Ops.push_back(V);
@@ -15705,10 +15711,6 @@ static SDValue performFP_TO_INTCombine(SDNode *N,
unsigned Opc =
IsSigned ? RISCVISD::VFCVT_RTZ_X_F_VL : RISCVISD::VFCVT_RTZ_XU_F_VL;
FpToInt = DAG.getNode(Opc, DL, ContainerVT, XVal, Mask, VL);
- } else if (FRM == RISCVFPRndMode::DYN) {
- unsigned Opc =
- IsSigned ? RISCVISD::VFCVT_X_F_VL : RISCVISD::VFCVT_XU_F_VL;
- FpToInt = DAG.getNode(Opc, DL, ContainerVT, XVal, Mask, VL);
} else {
unsigned Opc =
IsSigned ? RISCVISD::VFCVT_RM_X_F_VL : RISCVISD::VFCVT_RM_XU_F_VL;
@@ -20272,8 +20274,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(VFCVT_RTZ_XU_F_VL)
NODE_NAME_CASE(VFCVT_RM_X_F_VL)
NODE_NAME_CASE(VFCVT_RM_XU_F_VL)
- NODE_NAME_CASE(VFCVT_X_F_VL)
- NODE_NAME_CASE(VFCVT_XU_F_VL)
NODE_NAME_CASE(VFROUND_NOEXCEPT_VL)
NODE_NAME_CASE(SINT_TO_FP_VL)
NODE_NAME_CASE(UINT_TO_FP_VL)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 0b07ad7d7a423f..9ae70d257fa442 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -307,8 +307,6 @@ enum NodeType : unsigned {
FCOPYSIGN_VL, // Has a passthru operand
VFCVT_RTZ_X_F_VL,
VFCVT_RTZ_XU_F_VL,
- VFCVT_X_F_VL,
- VFCVT_XU_F_VL,
VFROUND_NOEXCEPT_VL,
VFCVT_RM_X_F_VL, // Has a rounding mode operand.
VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 33e1ed120cd086..9d434cef5a96f1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -270,8 +270,6 @@ def SDT_RISCVSETCCOP_VL : SDTypeProfile<1, 6, [
SDTCisSameAs<0, 5>, SDTCisVT<6, XLenVT>]>;
// Float -> Int
-def riscv_vfcvt_xu_f_vl : SDNode<"RISCVISD::VFCVT_XU_F_VL", SDT_RISCVFP2IOp_VL>;
-def riscv_vfcvt_x_f_vl : SDNode<"RISCVISD::VFCVT_X_F_VL", SDT_RISCVFP2IOp_VL>;
def riscv_vfcvt_rm_xu_f_vl : SDNode<"RISCVISD::VFCVT_RM_XU_F_VL", SDT_RISCVFP2IOp_RM_VL>;
def riscv_vfcvt_rm_x_f_vl : SDNode<"RISCVISD::VFCVT_RM_X_F_VL", SDT_RISCVFP2IOp_RM_VL>;
@@ -1206,24 +1204,6 @@ multiclass VPatConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> {
}
}
-multiclass VPatConvertFP2IVL_V_RM<SDPatternOperator vop, string instruction_name> {
- foreach fvti = AllFloatVectors in {
- defvar ivti = GetIntVTypeInfo<fvti>.Vti;
- let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
- GetVTypePredicates<ivti>.Predicates) in
- def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
- (fvti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
- (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
- (fvti.Mask V0),
- // Value to indicate no rounding mode change in
- // RISCVInsertReadWriteCSR
- FRM_DYN,
- GPR:$vl, ivti.Log2SEW, TA_MA)>;
- }
-}
-
multiclass VPatConvertFP2I_RM_VL_V<SDPatternOperator vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
@@ -1289,25 +1269,6 @@ multiclass VPatWConvertFP2IVL_V<SDPatternOperator vop, string instruction_name>
}
}
-multiclass VPatWConvertFP2IVL_V_RM<SDPatternOperator vop, string instruction_name> {
- foreach fvtiToFWti = AllWidenableFloatVectors in {
- defvar fvti = fvtiToFWti.Vti;
- defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
- let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
- GetVTypePredicates<iwti>.Predicates) in
- def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
- (fvti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
- (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
- (fvti.Mask V0),
- // Value to indicate no rounding mode change in
- // RISCVInsertReadWriteCSR
- FRM_DYN,
- GPR:$vl, fvti.Log2SEW, TA_MA)>;
- }
-}
-
multiclass VPatWConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
@@ -1361,28 +1322,6 @@ multiclass VPatNConvertFP2IVL_W<SDPatternOperator vop,
}
}
-multiclass VPatNConvertFP2IVL_W_RM<SDPatternOperator vop,
- string instruction_name> {
- // Reuse the same list of types used in the widening nodes, but just swap the
- // direction of types around so we're converting from Wti -> Vti
- foreach vtiToWti = AllWidenableIntToFloatVectors in {
- defvar vti = vtiToWti.Vti;
- defvar fwti = vtiToWti.Wti;
- let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
- GetVTypePredicates<fwti>.Predicates) in
- def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
- (fwti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK")
- (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
- (fwti.Mask V0),
- // Value to indicate no rounding mode change in
- // RISCVInsertReadWriteCSR
- FRM_DYN,
- GPR:$vl, vti.Log2SEW, TA_MA)>;
- }
-}
-
multiclass VPatNConvertFP2I_RM_VL_W<SDNode vop, string instruction_name> {
foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti;
@@ -2637,8 +2576,6 @@ foreach fvti = AllFloatVectors in {
}
// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
-defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFCVT_XU_F_V">;
-defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFCVT_X_F_V">;
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_XU_F_V">;
defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_X_F_V">;
@@ -2652,8 +2589,6 @@ defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_F_XU_V">;
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_F_X_V">;
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
-defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
-defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFWCVT_X_F_V">;
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_X_F_V">;
@@ -2694,8 +2629,6 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
}
// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
-defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
-defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_x_f_vl, "PseudoVFNCVT_X_F_W">;
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F_W">;
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