[llvm] [RISCV] fix SP recovery in varargs functions (PR #114316)

[via llvm-commits]

https://github.com/dlav-sc updated https://github.com/llvm/llvm-project/pull/114316

>From ebbd8a678beae0f78fd9e7a9c7820668b55a1818 Mon Sep 17 00:00:00 2001
From: Daniil Avdeev <daniil.avdeev at syntacore.com>
Date: Wed, 30 Oct 2024 21:07:49 +0000
Subject: [PATCH 1/2] [RISCV] fix SP recovery in varargs functions

---
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index f5851f37154519..2ff78ce9ea9c65 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -809,9 +809,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
   uint64_t StackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount
                                            : getStackSizeWithRVVPadding(MF) -
                                                  RVFI->getReservedSpillsSize();
-  uint64_t FPOffset = FirstSPAdjustAmount ? FirstSPAdjustAmount
-                                          : getStackSizeWithRVVPadding(MF) -
-                                                RVFI->getVarArgsSaveSize();
+  uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
   uint64_t RVVStackSize = RVFI->getRVVStackSize();
 
   bool RestoreFP = RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||

>From 49527f4931cd41db73fe1b10cd3a61a7e548ec59 Mon Sep 17 00:00:00 2001
From: Daniil Avdeev <daniil.avdeev at syntacore.com>
Date: Wed, 30 Oct 2024 21:09:44 +0000
Subject: [PATCH 2/2] [RISCV] add varargs SP recovery test

---
 llvm/test/CodeGen/RISCV/pr114316.ll | 46 +++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/pr114316.ll

diff --git a/llvm/test/CodeGen/RISCV/pr114316.ll b/llvm/test/CodeGen/RISCV/pr114316.ll
new file mode 100644
index 00000000000000..59a054609eb248
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr114316.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -riscv-v-vector-bits-max=512 -mtriple=riscv64 -mattr=+m,+c,+v -O0 < %s | FileCheck --check-prefix=RV64V %s
+
+declare void @llvm.va_copy.p0(ptr, ptr)
+declare void @llvm.va_end.p0(ptr)
+
+define dso_local void @_Z3fooPKcz(ptr noundef %0, ...) mustprogress noinline optnone uwtable vscale_range(8,8) "frame-pointer"="all" {
+; RV64V-LABEL: _Z3fooPKcz:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    addi sp, sp, -496
+; RV64V-NEXT:    .cfi_def_cfa_offset 496
+; RV64V-NEXT:    sd ra, 424(sp) # 8-byte Folded Spill
+; RV64V-NEXT:    sd s0, 416(sp) # 8-byte Folded Spill
+; RV64V-NEXT:    .cfi_offset ra, -72
+; RV64V-NEXT:    .cfi_offset s0, -80
+; RV64V-NEXT:    addi s0, sp, 432
+; RV64V-NEXT:    .cfi_def_cfa s0, 64
+; RV64V-NEXT:    lui t0, 2
+; RV64V-NEXT:    addiw t0, t0, -576
+; RV64V-NEXT:    sub sp, sp, t0
+; RV64V-NEXT:    sd a7, 56(s0)
+; RV64V-NEXT:    sd a6, 48(s0)
+; RV64V-NEXT:    sd a5, 40(s0)
+; RV64V-NEXT:    sd a4, 32(s0)
+; RV64V-NEXT:    sd a3, 24(s0)
+; RV64V-NEXT:    sd a2, 16(s0)
+; RV64V-NEXT:    sd a1, 8(s0)
+; RV64V-NEXT:    sd a0, -32(s0)
+; RV64V-NEXT:    addi a0, s0, 8
+; RV64V-NEXT:    sd a0, -40(s0)
+; RV64V-NEXT:    addi sp, s0, -432
+; RV64V-NEXT:    ld ra, 424(sp) # 8-byte Folded Reload
+; RV64V-NEXT:    ld s0, 416(sp) # 8-byte Folded Reload
+; RV64V-NEXT:    addi sp, sp, 496
+; RV64V-NEXT:    ret
+  %2 = alloca ptr, align 8
+  %3 = alloca ptr, align 8
+  %4 = alloca [8000 x i8], align 1
+  store ptr %0, ptr %2, align 8
+  call void @llvm.va_start.p0(ptr %3)
+  %5 = getelementptr inbounds [8000 x i8], ptr %4, i64 0, i64 0
+  %6 = load ptr, ptr %2, align 8
+  %7 = load ptr, ptr %3, align 8
+  call void @llvm.va_end.p0(ptr %3)
+  ret void
+}