[llvm] [AMDGPU] In instruction selector, allow copy from physical reg to s1 (PR #96157)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> For the problem we are dealing with here, ie. copy from a phys reg to a VCC reg, if you don't query the membership of the phys reg, how do you allow `%0:vcc(s1) = COPY $sgpr0` and disallow `%0:vcc(s1) = COPY $sgpr0_sgpr1`, or vice versa?

This depends on the wavesize. `%0:vcc(s1) = COPY $sgpr0` is only valid for wave32, and `%0:vcc(s1) = COPY $sgpr0_sgpr1` for wave64. We should reject in the machine verifier cases with the vcc bank and the wrong wavesize physical register 

https://github.com/llvm/llvm-project/pull/96157