[llvm] [SelectionDAG] Support integer promotion for VP_LOAD and VP_STORE (PR #81299)

[Craig Topper via llvm-commits]

================
@@ -2216,6 +2242,50 @@ SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
                            N->getMemoryVT(), N->getMemOperand());
 }
 
+SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
+                                                unsigned OpNo) {
+  SDValue DataOp = N->getValue();
+  SDValue Operand = N->getOperand(OpNo);
+
+  if (OpNo >= 4) {
+    // The Mask or EVL. Update in place.
+    EVT DataVT = DataOp.getValueType();
+    SDValue PromotedOperand = OpNo == 4 ? PromoteTargetBoolean(Operand, DataVT)
+                                        : ZExtPromotedInteger(Operand);
+    SmallVector<SDValue, 6> NewOps(N->op_begin(), N->op_end());
+    NewOps[OpNo] = PromotedOperand;
+    return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
+  }
+
+  assert(OpNo == 1 && "Unexpected operand for promotion");
+  DataOp = GetPromotedInteger(DataOp);
+
+  assert(!N->isIndexed() && "expecting unindexed vp_store!");
+
+  return DAG.getTruncStoreVP(N->getChain(), SDLoc(N), DataOp, N->getBasePtr(),
+                             N->getMask(), N->getVectorLength(),
+                             N->getMemoryVT(), N->getMemOperand(),
+                             N->isCompressingStore());
+}
+
+SDValue DAGTypeLegalizer::PromoteIntOp_VP_LOAD(VPLoadSDNode *N, unsigned OpNo) {
----------------
topperc wrote:

It's impossible to test. The mask for AArch64 and RISC-V never needs to be promoted. The VL operand is required to be legal when the node is constructed. SelectionDAGBuilder handles that by calling TLI.getVPExplicitVectorLengthTy().

This code can just be deleted. 

https://github.com/llvm/llvm-project/pull/81299