[llvm] c3724ba - [RISCV] Add OperandType for vector rounding mode operands. (#114179)
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Wed Oct 30 11:46:20 PDT 2024
Author: Craig Topper
Date: 2024-10-30T11:46:15-07:00
New Revision: c3724ba8667c695f29d5af93f2b0d1b23c1b41e7
URL: https://github.com/llvm/llvm-project/commit/c3724ba8667c695f29d5af93f2b0d1b23c1b41e7
DIFF: https://github.com/llvm/llvm-project/commit/c3724ba8667c695f29d5af93f2b0d1b23c1b41e7.diff
LOG: [RISCV] Add OperandType for vector rounding mode operands. (#114179)
Use TSFlags to distinquish which type of rounding mode it is. We use the same tablegen base classes for vxrm and frm sometimes so its hard to have different types for different instructions.
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index b3a6cd40ea039b..19103e219cb800 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -341,7 +341,9 @@ enum OperandType : unsigned {
OPERAND_VEC_POLICY,
// Vector SEW operand.
OPERAND_SEW,
- OPERAND_LAST_RISCV_IMM = OPERAND_SEW,
+ // Vector rounding mode for VXRM or FRM.
+ OPERAND_VEC_RM,
+ OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d5b086861d71e6..688da1ee1b33fb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2551,6 +2551,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_SEW:
Ok = Imm == 0 || (Imm >= 3 && Imm <= 6);
break;
+ case RISCVOp::OPERAND_VEC_RM:
+ assert(RISCVII::hasRoundModeOp(Desc.TSFlags));
+ if (RISCVII::usesVXRM(Desc.TSFlags))
+ Ok = isUInt<2>(Imm);
+ else
+ Ok = RISCVFPRndMode::isValidRoundingMode(Imm);
+ break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 5554fda760ebb9..399a2386d493e2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -92,6 +92,10 @@ def sew : RISCVOp {
let OperandType = "OPERAND_SEW";
}
+def vec_rm : RISCVOp {
+ let OperandType = "OPERAND_VEC_RM";
+}
+
// X0 has special meaning for vsetvl/vsetvli.
// rd | rs1 | AVL value | Effect on vl
//--------------------------------------------------------------
@@ -1057,7 +1061,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm,
+ (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
@@ -1097,7 +1101,7 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
bits<2> TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, ixlenimm:$rm,
+ VMaskOp:$vm, vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
@@ -1135,7 +1139,7 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
+ (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$frm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
@@ -1155,7 +1159,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
bits<2> TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, ixlenimm:$frm,
+ VMaskOp:$vm, vec_rm:$frm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
@@ -1250,7 +1254,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
bit UsesVXRM_ = 1,
bits<2> TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
+ (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
@@ -1273,7 +1277,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, ixlenimm:$rm, AVL:$vl,
+ VMaskOp:$vm, vec_rm:$rm, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
@@ -1317,7 +1321,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
bits<2> TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1,
- ixlenimm:$rm,
+ vec_rm:$rm,
AVL:$vl, sew:$sew,
vec_policy:$policy), []>,
RISCVVPseudo {
@@ -1408,7 +1412,7 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm,
- ixlenimm:$rm,
+ vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
@@ -1475,7 +1479,7 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op2Class:$rs1,
VMaskOp:$vm,
- ixlenimm:$rm,
+ vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
@@ -1578,7 +1582,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
bits<2> TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- ixlenimm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
+ vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
diff --git a/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll b/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
index ccfe94ecad286b..54f56eadf00342 100644
--- a/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
@@ -559,7 +559,7 @@ define <vscale x 1 x float> @after_fsrm3(<vscale x 1 x float> %0, <vscale x 1 x
; CHECK-LABEL: after_fsrm3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi 4
-; CHECK-NEXT: fsrmi a1, 5
+; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: fsrm a1
@@ -568,7 +568,7 @@ define <vscale x 1 x float> @after_fsrm3(<vscale x 1 x float> %0, <vscale x 1 x
; UNOPT-LABEL: after_fsrm3:
; UNOPT: # %bb.0: # %entry
; UNOPT-NEXT: fsrmi 4
-; UNOPT-NEXT: fsrmi a1, 5
+; UNOPT-NEXT: fsrmi a1, 3
; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; UNOPT-NEXT: vfadd.vv v8, v8, v9
; UNOPT-NEXT: fsrm a1
@@ -579,7 +579,7 @@ entry:
<vscale x 1 x float> undef,
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
- i64 5, i64 %2)
+ i64 3, i64 %2)
ret <vscale x 1 x float> %a
}
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