[llvm] [AArch64] Add @llvm.experimental.vector.match (PR #101974)

[Paul Walker via llvm-commits]

================
@@ -4072,6 +4072,23 @@ bool AArch64TTIImpl::isLegalToVectorizeReduction(
   }
 }
 
+bool AArch64TTIImpl::hasVectorMatch(VectorType *VT, unsigned SearchSize) const {
+  // Check that the target has SVE2 and SVE is available.
+  if (!ST->hasSVE2() || !ST->isSVEAvailable())
+    return false;
+
+  // Check that `VT' is a legal type for MATCH, and that the search vector can
+  // be broadcast efficently if necessary.
+  // Currently, we require the search vector to be 64-bit or 128-bit. In the
+  // future we can generalise this to other lengths.
+  unsigned MinEC = VT->getElementCount().getKnownMinValue();
+  if ((MinEC == 8 || MinEC == 16) &&
+      VT->getPrimitiveSizeInBits().getKnownMinValue() == 128 &&
+      (MinEC == SearchSize || MinEC / 2 == SearchSize))
+    return true;
----------------
paulwalker-arm wrote:

This seems a little convoluted when compared to what you actually mean.  It looks like you're relying on the element count maths to verify the element types are of the correct size, whereas it will be clearer to explicit test the result of getVectorElementType().

Once that's done I'm wondering if the remaining logic can be accomplished with an `istypeLegal()` check? which opens the way for using `match` when using SVE fixed length vectors.

Alternative, and perhaps even cleaner is to just match the specific EVT you require, which I believe is something like:

```
if (NeedleVT != v16i8 && NeedleVT != v8i16)
  return false

if (SearchVT != nxv16i8 && NeedleVT != nxv8i16 && SearchVT != v16i8 && NeedleVT != v8i16)
  return false;
```

Some of this likely means passing in both vector types as EVT, but I see that as a better interface for what's effectively a code generation question anyway.

https://github.com/llvm/llvm-project/pull/101974