[llvm] AMDGPU: Disable pattern matching "x<<32-y>>32-y" to "bfe x, 0, y" (PR #114279)

[Matt Arsenault via llvm-commits]

arsenm wrote:

But yes, this form doesn't appear canonically. We are missing a fold here though:

```

define i32 @tgt(i32 %unscaled, i32 %size) {
  %src2.clamp.i = and i32 %size, 31
  %shl.src2.i = shl i32 1, %src2.clamp.i
  %rhs.i = sub i32 %shl.src2.i, 1
  %and.i = and i32 %unscaled, %rhs.i
  ret i32 %and.i
}

```
Produces:
```
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_and_b32_e32 v1, 31, v1
	v_bfe_u32 v0, v0, 0, v1
	s_setpc_b64 s[30:31]
```

We should be able to fold out the and, we know the instruction only reads the low 5 bits 

https://github.com/llvm/llvm-project/pull/114279