[llvm] [TableGen] Make `!and` short-circuit when either of the operand is zero (PR #113963)

[Min-Yih Hsu via llvm-commits]

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@@ -1543,6 +1543,23 @@ const Init *BinOpInit::resolveReferences(Resolver &R) const {
   const Init *lhs = LHS->resolveReferences(R);
   const Init *rhs = RHS->resolveReferences(R);
 
+  if (getOpcode() == AND) {
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mshockwave wrote:

> Good point, I had thought this before. The problem is that since `!or` is for both logical and bitwise operation, we can't short circuit something like this `!or(true, <unknown / unresolved>)` until the second operand is resolved (in which case it's not a short circuit anymore) because we're not sure if the second operand is a int (bitwise OR) or a bit (logical OR).

I just made a blunder and forgot that `!or(<all ones>, ...)` can also be short-circuited. I'll add this case into this patch as well.

https://github.com/llvm/llvm-project/pull/113963