[llvm] [RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid (PR #114250)

[Philip Reames via llvm-commits]

================
@@ -1523,9 +1523,17 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
       ISD != ISD::FADD)
     return BaseT::getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
 
+  Type *ElementTy = Ty->getElementType();
+  // We can't promote f16/bf16 fadd reductions.
+  if (ISD == ISD::FADD &&
----------------
preames wrote:

The previous version of the code was written in terms of legalized types, the new one in terms of the IR type.  Maybe keep the legalized version to avoid potential edge cases?  (None specifically known to me.)

https://github.com/llvm/llvm-project/pull/114250