[llvm] [RISCV] Only calculate ordered reduction with FloatingPoint type. NFC (PR #114180)

[Philip Reames via llvm-commits]

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@@ -1552,7 +1552,7 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
   }
 
   // IR Reduction is composed by two vmv and one rvv reduction instruction.
-  if (TTI::requiresOrderedReduction(FMF)) {
+  if (TTI::requiresOrderedReduction(FMF) && ElementTy->isFloatingPointTy()) {
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preames wrote:

I think a cleaner way to express this change is to simply sink the check for requiresOrderedReduction under the FADD case in the switch below.  That's the only supported reduction kind with an ordered variant.  

https://github.com/llvm/llvm-project/pull/114180